Lines Matching defs:ro
30 * @ro: Read-Only bits
41 u32 ro;
52 [PCI_VENDOR_ID / 4] = { .ro = ~0 },
57 .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
64 [PCI_CLASS_REVISION / 4] = { .ro = ~0 },
82 [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
88 [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
89 [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
95 .ro = GENMASK(31, 24),
103 .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
115 .ro = GENMASK(19, 16) | GENMASK(3, 0),
123 .ro = GENMASK(19, 16) | GENMASK(3, 0),
139 .ro = GENMASK(7, 0),
148 .ro = ~0,
168 .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
182 .ro = GENMASK(30, 0),
192 .ro = BIT(15) | GENMASK(5, 0),
208 .ro = GENMASK(5, 4) << 16,
216 .ro = lower_32_bits(~(BIT(23) | PCI_EXP_LNKCAP_CLKPM)),
228 .ro = GENMASK(13, 0) << 16,
233 .ro = ~0,
248 .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
262 .ro = PCI_EXP_RTCAP_CRSVIS << 16,
270 .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
311 bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
313 bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
319 bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
321 bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
327 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
334 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
402 *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |