Lines Matching refs:ctrl
169 static void start_int_poll_timer(struct controller *ctrl, int sec);
170 static int hpc_check_cmd_status(struct controller *ctrl);
172 static inline u8 shpc_readb(struct controller *ctrl, int reg)
174 return readb(ctrl->creg + reg);
177 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
179 writeb(val, ctrl->creg + reg);
182 static inline u16 shpc_readw(struct controller *ctrl, int reg)
184 return readw(ctrl->creg + reg);
187 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
189 writew(val, ctrl->creg + reg);
192 static inline u32 shpc_readl(struct controller *ctrl, int reg)
194 return readl(ctrl->creg + reg);
197 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
199 writel(val, ctrl->creg + reg);
202 static inline int shpc_indirect_read(struct controller *ctrl, int index,
206 u32 cap_offset = ctrl->cap_offset;
207 struct pci_dev *pdev = ctrl->pci_dev;
220 struct controller *ctrl = from_timer(ctrl, t, poll_timer);
223 shpc_isr(0, ctrl);
228 start_int_poll_timer(ctrl, shpchp_poll_time);
234 static void start_int_poll_timer(struct controller *ctrl, int sec)
240 ctrl->poll_timer.expires = jiffies + sec * HZ;
241 add_timer(&ctrl->poll_timer);
244 static inline int is_ctrl_busy(struct controller *ctrl)
246 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
254 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
258 if (!is_ctrl_busy(ctrl))
264 if (!is_ctrl_busy(ctrl))
271 static inline int shpc_wait_cmd(struct controller *ctrl)
278 rc = shpc_poll_ctrl_busy(ctrl);
280 rc = wait_event_interruptible_timeout(ctrl->queue,
281 !is_ctrl_busy(ctrl), timeout);
282 if (!rc && is_ctrl_busy(ctrl)) {
284 ctrl_err(ctrl, "Command not completed in 1000 msec\n");
287 ctrl_info(ctrl, "Command was interrupted by a signal\n");
295 struct controller *ctrl = slot->ctrl;
300 mutex_lock(&slot->ctrl->cmd_lock);
302 if (!shpc_poll_ctrl_busy(ctrl)) {
304 ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
311 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
316 shpc_writew(ctrl, CMD, temp_word);
321 retval = shpc_wait_cmd(slot->ctrl);
325 cmd_status = hpc_check_cmd_status(slot->ctrl);
327 ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n",
332 mutex_unlock(&slot->ctrl->cmd_lock);
336 static int hpc_check_cmd_status(struct controller *ctrl)
339 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
347 ctrl_err(ctrl, "Switch opened!\n");
351 ctrl_err(ctrl, "Invalid HPC command!\n");
355 ctrl_err(ctrl, "Invalid bus speed/mode!\n");
367 struct controller *ctrl = slot->ctrl;
368 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
391 struct controller *ctrl = slot->ctrl;
392 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
416 struct controller *ctrl = slot->ctrl;
417 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
426 struct controller *ctrl = slot->ctrl;
427 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
437 struct controller *ctrl = slot->ctrl;
439 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
447 struct controller *ctrl = slot->ctrl;
448 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
467 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
493 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
500 struct controller *ctrl = slot->ctrl;
501 u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
502 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
510 ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);
516 struct controller *ctrl = slot->ctrl;
517 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
560 static void hpc_release_ctlr(struct controller *ctrl)
568 for (i = 0; i < ctrl->num_slots; i++) {
569 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
575 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
578 cleanup_slots(ctrl);
583 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
587 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
590 del_timer(&ctrl->poll_timer);
592 free_irq(ctrl->pci_dev->irq, ctrl);
593 pci_disable_msi(ctrl->pci_dev);
596 iounmap(ctrl->creg);
597 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
606 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
619 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
632 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
637 static int shpc_get_cur_bus_speed(struct controller *ctrl)
640 struct pci_bus *bus = ctrl->pci_dev->subordinate;
642 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
643 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
709 struct controller *ctrl = slot->ctrl;
712 pi = shpc_readb(ctrl, PROG_INTERFACE);
765 ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
767 shpc_get_cur_bus_speed(ctrl);
774 struct controller *ctrl = (struct controller *)dev_id;
779 intr_loc = shpc_readl(ctrl, INTR_LOC);
783 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
790 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
793 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
795 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
796 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
805 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
807 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
809 wake_up_interruptible(&ctrl->queue);
815 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
820 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
821 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
825 shpchp_handle_switch_change(hp_slot, ctrl);
828 shpchp_handle_attention_button(hp_slot, ctrl);
831 shpchp_handle_presence_change(hp_slot, ctrl);
834 shpchp_handle_power_fault(hp_slot, ctrl);
838 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
843 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
845 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
851 static int shpc_get_max_bus_speed(struct controller *ctrl)
854 struct pci_bus *bus = ctrl->pci_dev->subordinate;
856 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
857 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
858 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
891 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
919 int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
927 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
928 ctrl_dbg(ctrl, "Hotplug Controller:\n");
933 ctrl->mmio_base = pci_resource_start(pdev, 0);
934 ctrl->mmio_size = pci_resource_len(pdev, 0);
936 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
937 if (!ctrl->cap_offset) {
938 ctrl_err(ctrl, "Cannot find PCI capability\n");
941 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
943 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
945 ctrl_err(ctrl, "Cannot read base_offset\n");
949 rc = shpc_indirect_read(ctrl, 3, &tempdword);
951 ctrl_err(ctrl, "Cannot read slot config\n");
955 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
958 rc = shpc_indirect_read(ctrl, i, &tempdword);
960 ctrl_err(ctrl, "Cannot read creg (index = %d)\n",
964 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
967 ctrl->mmio_base =
969 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
972 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
978 ctrl_err(ctrl, "pci_enable_device failed\n");
982 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
983 ctrl_err(ctrl, "Cannot reserve MMIO region\n");
988 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
989 if (!ctrl->creg) {
990 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
991 ctrl->mmio_size, ctrl->mmio_base);
992 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
996 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
998 mutex_init(&ctrl->crit_sect);
999 mutex_init(&ctrl->cmd_lock);
1002 init_waitqueue_head(&ctrl->queue);
1004 ctrl->hpc_ops = &shpchp_hpc_ops;
1007 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1008 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1009 ctrl->num_slots = slot_config & SLOT_NUM;
1010 ctrl->first_slot = (slot_config & PSN) >> 16;
1011 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
1014 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1015 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1019 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1020 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1021 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1026 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1027 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1028 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1035 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1040 timer_setup(&ctrl->poll_timer, int_poll_timeout, 0);
1041 start_int_poll_timer(ctrl, 10);
1046 ctrl_info(ctrl, "Can't get msi for the hotplug controller\n");
1047 ctrl_info(ctrl, "Use INTx for the hotplug controller\n");
1052 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1053 MY_NAME, (void *)ctrl);
1054 ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",
1055 ctrl->pci_dev->irq, rc);
1057 ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n",
1058 ctrl->pci_dev->irq);
1062 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
1064 shpc_get_max_bus_speed(ctrl);
1065 shpc_get_cur_bus_speed(ctrl);
1070 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1071 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1072 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1077 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1081 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1084 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1085 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1086 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1093 iounmap(ctrl->creg);