Lines Matching refs:ctrl
48 #define ctrl_dbg(ctrl, format, arg...) \
51 pci_printk(KERN_DEBUG, ctrl->pci_dev, \
54 #define ctrl_err(ctrl, format, arg...) \
55 pci_err(ctrl->pci_dev, format, ## arg)
56 #define ctrl_info(ctrl, format, arg...) \
57 pci_info(ctrl->pci_dev, format, ## arg)
58 #define ctrl_warn(ctrl, format, arg...) \
59 pci_warn(ctrl->pci_dev, format, ## arg)
74 struct controller *ctrl;
158 int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
159 void shpchp_remove_ctrl_files(struct controller *ctrl);
162 u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
163 u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
164 u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
165 u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
168 void cleanup_slots(struct controller *ctrl);
170 int shpc_init(struct controller *ctrl, struct pci_dev *pdev);
215 static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
219 list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
224 ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
233 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
235 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
243 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
255 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
258 ctrl_dbg(p_slot->ctrl,
262 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
266 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
269 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
271 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
274 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
276 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
281 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
286 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
291 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
296 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
300 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
320 void (*release_ctlr)(struct controller *ctrl);
321 int (*check_cmd_status)(struct controller *ctrl);