Lines Matching refs:base
543 * Saves the length of all base address registers for the
556 u32 base;
590 * IO and memory base lengths
595 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
597 if (base) {
598 if (base & 0x01L) {
599 /* IO base
600 * set base = amount of IO space
603 base = base & 0xFFFFFFFE;
604 base = (~base) + 1;
608 /* memory base */
609 base = base & 0xFFFFFFF0;
610 base = (~base) + 1;
615 base = 0x0L;
621 base;
624 } /* End of base register loop */
627 /* Figure out IO and memory base lengths */
631 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
634 if (base) {
635 if (base & 0x01L) {
636 /* IO base
637 * base = amount of IO space
640 base = base & 0xFFFFFFFE;
641 base = (~base) + 1;
645 /* memory base
646 * base = amount of memory
649 base = base & 0xFFFFFFF0;
650 base = (~base) + 1;
655 base = 0x0L;
660 func->base_length[(cloop - 0x10) >> 2] = base;
663 } /* End of base register loop */
699 u32 base;
735 bus_node->base = secondary_bus;
741 /* Save IO base and Limit registers */
750 io_node->base = (b_base & 0xF0) << 8;
757 /* Save memory base and Limit registers */
766 mem_node->base = w_base << 16;
773 /* Save prefetchable memory base and Limit registers */
782 p_mem_node->base = w_base << 16;
788 /* Figure out IO and memory base lengths */
794 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
796 temp_register = base;
799 if (base) {
800 if (((base & 0x03L) == 0x01)
802 /* IO base
806 temp_register = base & 0xFFFFFFFE;
814 io_node->base =
821 if (((base & 0x0BL) == 0x08)
823 /* prefetchable memory base */
824 temp_register = base & 0xFFFFFFF0;
832 p_mem_node->base = save_base & (~0x0FL);
838 if (((base & 0x0BL) == 0x00)
840 /* prefetchable memory base */
841 temp_register = base & 0xFFFFFFF0;
849 mem_node->base = save_base & (~0x0FL);
857 } /* End of base register loop */
860 /* Figure out IO and memory base lengths */
866 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
868 temp_register = base;
871 if (base) {
872 if (((base & 0x03L) == 0x01)
874 /* IO base
878 temp_register = base & 0xFFFFFFFE;
886 io_node->base = save_base & (~0x01L);
892 if (((base & 0x0BL) == 0x08)
894 /* prefetchable memory base */
895 temp_register = base & 0xFFFFFFF0;
903 p_mem_node->base = save_base & (~0x0FL);
909 if (((base & 0x0BL) == 0x00)
911 /* prefetchable memory base */
912 temp_register = base & 0xFFFFFFF0;
920 mem_node->base = save_base & (~0x0FL);
928 } /* End of base register loop */
992 /* Check all the base Address Registers to make sure
1033 u32 base;
1104 /* Figure out IO and memory base lengths */
1108 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
1111 if (base) {
1112 if (base & 0x01L) {
1113 /* IO base
1114 * set base = amount of IO
1117 base = base & 0xFFFFFFFE;
1118 base = (~base) + 1;
1122 /* memory base */
1123 base = base & 0xFFFFFFF0;
1124 base = (~base) + 1;
1129 base = 0x0L;
1134 if (func->base_length[(cloop - 0x10) >> 2] != base)
1140 } /* End of base register loop */
1241 dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n");
1298 /* If we've got a valid IO base, use it */
1307 io_node->base = io_base;
1310 dbg("found io_node(base, length) = %x, %x\n",
1311 io_node->base, io_node->length);
1322 /* If we've got a valid memory base, use it */
1329 mem_node->base = mem_base << 16;
1333 dbg("found mem_node(base, length) = %x, %x\n",
1334 mem_node->base, mem_node->length);
1345 /* If we've got a valid prefetchable memory base, and
1346 * the base + length isn't greater than 0xFFFF
1354 p_mem_node->base = pre_mem_base << 16;
1357 dbg("found p_mem_node(base, length) = %x, %x\n",
1358 p_mem_node->base, p_mem_node->length);
1379 bus_node->base = secondary_bus;
1381 dbg("found bus_node(base, length) = %x, %x\n",
1382 bus_node->base, bus_node->length);