Lines Matching refs:pcie
4 * Based on pcie-xilinx.c, pci-tegra.c
176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
178 return readl(pcie->breg_base + off);
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
183 writel(val, pcie->breg_base + off);
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
200 static int nwl_wait_for_link(struct nwl_pcie *pcie)
202 struct device *dev = pcie->dev;
207 if (nwl_phy_link_up(pcie))
218 struct nwl_pcie *pcie = bus->sysdata;
222 if (!nwl_pcie_link_up(pcie))
244 struct nwl_pcie *pcie = bus->sysdata;
253 return pcie->ecam_base + relbus + where;
265 struct nwl_pcie *pcie = data;
266 struct device *dev = pcie->dev;
270 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
315 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
323 struct nwl_pcie *pcie;
329 pcie = irq_desc_get_handler_data(desc);
331 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
334 virq = irq_find_mapping(pcie->legacy_irq_domain, bit);
343 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
350 msi = &pcie->msi;
352 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
354 nwl_bridge_writel(pcie, 1 << bit, status_reg);
365 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
368 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
375 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
378 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
385 struct nwl_pcie *pcie;
390 pcie = irq_desc_get_chip_data(desc);
392 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
393 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
394 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
395 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
401 struct nwl_pcie *pcie;
406 pcie = irq_desc_get_chip_data(desc);
408 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
409 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
410 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
411 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
455 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
456 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
478 struct nwl_pcie *pcie = domain->host_data;
479 struct nwl_msi *msi = &pcie->msi;
504 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
505 struct nwl_msi *msi = &pcie->msi;
518 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
521 struct device *dev = pcie->dev;
523 struct nwl_msi *msi = &pcie->msi;
526 &dev_msi_domain_ops, pcie);
543 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
545 struct device *dev = pcie->dev;
555 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
558 pcie);
560 if (!pcie->legacy_irq_domain) {
565 raw_spin_lock_init(&pcie->leg_mask_lock);
566 nwl_pcie_init_msi_irq_domain(pcie);
570 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
572 struct device *dev = pcie->dev;
574 struct nwl_msi *msi = &pcie->msi;
593 nwl_pcie_msi_handler_high, pcie);
603 nwl_pcie_msi_handler_low, pcie);
606 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
614 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
618 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
622 base = pcie->phys_pcie_reg_base;
623 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
624 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
630 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
632 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
635 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
641 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
643 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
646 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
655 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
657 struct device *dev = pcie->dev;
662 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
669 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
671 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
675 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
679 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
683 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
686 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
689 err = nwl_wait_for_link(pcie);
693 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
700 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
703 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
704 (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
707 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
709 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
713 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
714 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
718 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
719 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
721 if (nwl_pcie_link_up(pcie))
727 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
728 if (pcie->irq_misc < 0)
731 err = devm_request_irq(dev, pcie->irq_misc,
733 "nwl_pcie:misc", pcie);
736 pcie->irq_misc);
741 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
744 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
748 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
752 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
755 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
759 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
762 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
768 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
771 struct device *dev = pcie->dev;
775 pcie->breg_base = devm_ioremap_resource(dev, res);
776 if (IS_ERR(pcie->breg_base))
777 return PTR_ERR(pcie->breg_base);
778 pcie->phys_breg_base = res->start;
781 pcie->pcireg_base = devm_ioremap_resource(dev, res);
782 if (IS_ERR(pcie->pcireg_base))
783 return PTR_ERR(pcie->pcireg_base);
784 pcie->phys_pcie_reg_base = res->start;
787 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
788 if (IS_ERR(pcie->ecam_base))
789 return PTR_ERR(pcie->ecam_base);
790 pcie->phys_ecam_base = res->start;
793 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
794 if (pcie->irq_intx < 0)
795 return pcie->irq_intx;
797 irq_set_chained_handler_and_data(pcie->irq_intx,
798 nwl_pcie_leg_handler, pcie);
804 { .compatible = "xlnx,nwl-pcie-2.11", },
811 struct nwl_pcie *pcie;
815 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
819 pcie = pci_host_bridge_priv(bridge);
821 pcie->dev = dev;
822 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
824 err = nwl_pcie_parse_dt(pcie, pdev);
830 pcie->clk = devm_clk_get(dev, NULL);
831 if (IS_ERR(pcie->clk))
832 return PTR_ERR(pcie->clk);
834 err = clk_prepare_enable(pcie->clk);
840 err = nwl_pcie_bridge_init(pcie);
846 err = nwl_pcie_init_irq_domain(pcie);
852 bridge->sysdata = pcie;
856 err = nwl_pcie_enable_msi(pcie);
868 .name = "nwl-pcie",