Lines Matching refs:rockchip
24 #include "pcie-rockchip.h"
26 int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
28 struct device *dev = rockchip->dev;
34 if (rockchip->is_rc) {
38 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
39 if (IS_ERR(rockchip->reg_base))
40 return PTR_ERR(rockchip->reg_base);
42 rockchip->mem_res =
45 if (!rockchip->mem_res)
49 rockchip->apb_base =
51 if (IS_ERR(rockchip->apb_base))
52 return PTR_ERR(rockchip->apb_base);
54 err = rockchip_pcie_get_phys(rockchip);
58 rockchip->lanes = 1;
59 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
60 if (!err && (rockchip->lanes == 0 ||
61 rockchip->lanes == 3 ||
62 rockchip->lanes > 4)) {
64 rockchip->lanes = 1;
67 rockchip->link_gen = of_pci_get_max_link_speed(node);
68 if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
69 rockchip->link_gen = 2;
71 rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
72 if (IS_ERR(rockchip->core_rst)) {
73 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
75 return PTR_ERR(rockchip->core_rst);
78 rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
79 if (IS_ERR(rockchip->mgmt_rst)) {
80 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
82 return PTR_ERR(rockchip->mgmt_rst);
85 rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
87 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
88 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
90 return PTR_ERR(rockchip->mgmt_sticky_rst);
93 rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
94 if (IS_ERR(rockchip->pipe_rst)) {
95 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
97 return PTR_ERR(rockchip->pipe_rst);
100 rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
101 if (IS_ERR(rockchip->pm_rst)) {
102 if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
104 return PTR_ERR(rockchip->pm_rst);
107 rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
108 if (IS_ERR(rockchip->pclk_rst)) {
109 if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
111 return PTR_ERR(rockchip->pclk_rst);
114 rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
115 if (IS_ERR(rockchip->aclk_rst)) {
116 if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
118 return PTR_ERR(rockchip->aclk_rst);
121 if (rockchip->is_rc) {
122 rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",
124 if (IS_ERR(rockchip->ep_gpio))
125 return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio),
129 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
130 if (IS_ERR(rockchip->aclk_pcie)) {
132 return PTR_ERR(rockchip->aclk_pcie);
135 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
136 if (IS_ERR(rockchip->aclk_perf_pcie)) {
138 return PTR_ERR(rockchip->aclk_perf_pcie);
141 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
142 if (IS_ERR(rockchip->hclk_pcie)) {
144 return PTR_ERR(rockchip->hclk_pcie);
147 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
148 if (IS_ERR(rockchip->clk_pcie_pm)) {
150 return PTR_ERR(rockchip->clk_pcie_pm);
157 #define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr)
163 int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
165 struct device *dev = rockchip->dev;
169 err = reset_control_assert(rockchip->aclk_rst);
175 err = reset_control_assert(rockchip->pclk_rst);
181 err = reset_control_assert(rockchip->pm_rst);
188 err = phy_init(rockchip->phys[i]);
195 err = reset_control_assert(rockchip->core_rst);
201 err = reset_control_assert(rockchip->mgmt_rst);
207 err = reset_control_assert(rockchip->mgmt_sticky_rst);
213 err = reset_control_assert(rockchip->pipe_rst);
221 err = reset_control_deassert(rockchip->pm_rst);
227 err = reset_control_deassert(rockchip->aclk_rst);
233 err = reset_control_deassert(rockchip->pclk_rst);
239 if (rockchip->link_gen == 2)
240 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
243 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
247 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);
249 if (rockchip->is_rc)
254 rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG);
257 err = phy_power_on(rockchip->phys[i]);
278 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
284 err = reset_control_deassert(rockchip->core_rst);
290 err = reset_control_deassert(rockchip->mgmt_rst);
296 err = reset_control_deassert(rockchip->pipe_rst);
305 phy_power_off(rockchip->phys[i]);
309 phy_exit(rockchip->phys[i]);
314 int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip)
316 struct device *dev = rockchip->dev;
323 rockchip->legacy_phy = true;
324 rockchip->phys[0] = phy;
349 rockchip->phys[i] = phy;
356 void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip)
362 if (rockchip->lanes_map & BIT(i))
363 phy_power_off(rockchip->phys[i]);
364 phy_exit(rockchip->phys[i]);
369 int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
371 struct device *dev = rockchip->dev;
374 err = clk_prepare_enable(rockchip->aclk_pcie);
380 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
386 err = clk_prepare_enable(rockchip->hclk_pcie);
392 err = clk_prepare_enable(rockchip->clk_pcie_pm);
401 clk_disable_unprepare(rockchip->hclk_pcie);
403 clk_disable_unprepare(rockchip->aclk_perf_pcie);
405 clk_disable_unprepare(rockchip->aclk_pcie);
412 struct rockchip_pcie *rockchip = data;
414 clk_disable_unprepare(rockchip->clk_pcie_pm);
415 clk_disable_unprepare(rockchip->hclk_pcie);
416 clk_disable_unprepare(rockchip->aclk_perf_pcie);
417 clk_disable_unprepare(rockchip->aclk_pcie);
422 struct rockchip_pcie *rockchip, u32 type)
427 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
429 rockchip_pcie_write(rockchip,
432 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
434 ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0);
437 rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0);
438 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);