Lines Matching defs:err
32 int err;
54 err = rockchip_pcie_get_phys(rockchip);
55 if (err)
56 return err;
59 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
60 if (!err && (rockchip->lanes == 0 ||
166 int err, i;
169 err = reset_control_assert(rockchip->aclk_rst);
170 if (err) {
171 dev_err(dev, "assert aclk_rst err %d\n", err);
172 return err;
175 err = reset_control_assert(rockchip->pclk_rst);
176 if (err) {
177 dev_err(dev, "assert pclk_rst err %d\n", err);
178 return err;
181 err = reset_control_assert(rockchip->pm_rst);
182 if (err) {
183 dev_err(dev, "assert pm_rst err %d\n", err);
184 return err;
188 err = phy_init(rockchip->phys[i]);
189 if (err) {
190 dev_err(dev, "init phy%d err %d\n", i, err);
195 err = reset_control_assert(rockchip->core_rst);
196 if (err) {
197 dev_err(dev, "assert core_rst err %d\n", err);
201 err = reset_control_assert(rockchip->mgmt_rst);
202 if (err) {
203 dev_err(dev, "assert mgmt_rst err %d\n", err);
207 err = reset_control_assert(rockchip->mgmt_sticky_rst);
208 if (err) {
209 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
213 err = reset_control_assert(rockchip->pipe_rst);
214 if (err) {
215 dev_err(dev, "assert pipe_rst err %d\n", err);
221 err = reset_control_deassert(rockchip->pm_rst);
222 if (err) {
223 dev_err(dev, "deassert pm_rst err %d\n", err);
227 err = reset_control_deassert(rockchip->aclk_rst);
228 if (err) {
229 dev_err(dev, "deassert aclk_rst err %d\n", err);
233 err = reset_control_deassert(rockchip->pclk_rst);
234 if (err) {
235 dev_err(dev, "deassert pclk_rst err %d\n", err);
257 err = phy_power_on(rockchip->phys[i]);
258 if (err) {
259 dev_err(dev, "power on phy%d err %d\n", i, err);
264 err = readx_poll_timeout(rockchip_pcie_read_addr,
269 if (err) {
270 dev_err(dev, "PHY PLLs could not lock, %d\n", err);
278 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
279 if (err) {
280 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
284 err = reset_control_deassert(rockchip->core_rst);
285 if (err) {
286 dev_err(dev, "deassert core_rst err %d\n", err);
290 err = reset_control_deassert(rockchip->mgmt_rst);
291 if (err) {
292 dev_err(dev, "deassert mgmt_rst err %d\n", err);
296 err = reset_control_deassert(rockchip->pipe_rst);
297 if (err) {
298 dev_err(dev, "deassert pipe_rst err %d\n", err);
310 return err;
372 int err;
374 err = clk_prepare_enable(rockchip->aclk_pcie);
375 if (err) {
377 return err;
380 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
381 if (err) {
386 err = clk_prepare_enable(rockchip->hclk_pcie);
387 if (err) {
392 err = clk_prepare_enable(rockchip->clk_pcie_pm);
393 if (err) {
406 return err;