Lines Matching refs:rockchip
40 #include "pcie-rockchip.h"
42 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
46 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
48 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
51 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
55 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
57 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
60 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
65 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
68 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
71 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
85 static u8 rockchip_pcie_lane_map(struct rockchip_pcie *rockchip)
90 if (rockchip->legacy_phy)
93 val = rockchip_pcie_read(rockchip, PCIE_CORE_LANE_MAP);
103 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
108 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where;
128 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
135 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset;
156 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
171 rockchip_pcie_cfg_configuration_accesses(rockchip,
174 rockchip_pcie_cfg_configuration_accesses(rockchip,
178 *val = readl(rockchip->reg_base + busdev);
180 *val = readw(rockchip->reg_base + busdev);
182 *val = readb(rockchip->reg_base + busdev);
190 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
202 rockchip_pcie_cfg_configuration_accesses(rockchip,
205 rockchip_pcie_cfg_configuration_accesses(rockchip,
209 writel(val, rockchip->reg_base + busdev);
211 writew(val, rockchip->reg_base + busdev);
213 writeb(val, rockchip->reg_base + busdev);
223 struct rockchip_pcie *rockchip = bus->sysdata;
225 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
231 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
233 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size,
240 struct rockchip_pcie *rockchip = bus->sysdata;
242 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
246 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
248 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size,
257 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
262 if (IS_ERR(rockchip->vpcie3v3))
271 curr = regulator_get_current_limit(rockchip->vpcie3v3);
280 dev_warn(rockchip->dev, "invalid power supply\n");
287 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
290 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
295 * @rockchip: PCIe port information
297 static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
299 struct device *dev = rockchip->dev;
303 gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
305 err = rockchip_pcie_init_port(rockchip);
310 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
313 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
315 rockchip_pcie_set_power_limit(rockchip);
318 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
320 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
323 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
325 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
328 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
331 gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
334 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
342 if (rockchip->link_gen == 2) {
347 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
349 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
351 err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
359 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
365 rockchip->lanes_map = rockchip_pcie_lane_map(rockchip);
367 if (!(rockchip->lanes_map & BIT(i))) {
369 phy_power_off(rockchip->phys[i]);
373 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
375 rockchip_pcie_write(rockchip,
380 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
382 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
386 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP);
388 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
391 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR);
394 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR);
399 phy_power_off(rockchip->phys[i]);
402 phy_exit(rockchip->phys[i]);
408 struct rockchip_pcie *rockchip = arg;
409 struct device *dev = rockchip->dev;
413 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
416 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
459 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
462 rockchip_pcie_update_txcredit_mui(rockchip);
463 rockchip_pcie_clr_bw_int(rockchip);
466 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
474 struct rockchip_pcie *rockchip = arg;
475 struct device *dev = rockchip->dev;
478 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
503 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
517 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
518 struct device *dev = rockchip->dev;
525 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
532 virq = irq_find_mapping(rockchip->irq_domain, hwirq);
542 static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)
545 struct device *dev = rockchip->dev;
553 IRQF_SHARED, "pcie-sys", rockchip);
565 rockchip);
572 IRQF_SHARED, "pcie-client", rockchip);
583 * @rockchip: PCIe port information
587 static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip)
589 struct device *dev = rockchip->dev;
592 err = rockchip_pcie_parse_dt(rockchip);
596 rockchip->vpcie12v = devm_regulator_get_optional(dev, "vpcie12v");
597 if (IS_ERR(rockchip->vpcie12v)) {
598 if (PTR_ERR(rockchip->vpcie12v) != -ENODEV)
599 return PTR_ERR(rockchip->vpcie12v);
603 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
604 if (IS_ERR(rockchip->vpcie3v3)) {
605 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
606 return PTR_ERR(rockchip->vpcie3v3);
610 rockchip->vpcie1v8 = devm_regulator_get(dev, "vpcie1v8");
611 if (IS_ERR(rockchip->vpcie1v8))
612 return PTR_ERR(rockchip->vpcie1v8);
614 rockchip->vpcie0v9 = devm_regulator_get(dev, "vpcie0v9");
615 if (IS_ERR(rockchip->vpcie0v9))
616 return PTR_ERR(rockchip->vpcie0v9);
621 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
623 struct device *dev = rockchip->dev;
626 if (!IS_ERR(rockchip->vpcie12v)) {
627 err = regulator_enable(rockchip->vpcie12v);
634 if (!IS_ERR(rockchip->vpcie3v3)) {
635 err = regulator_enable(rockchip->vpcie3v3);
642 err = regulator_enable(rockchip->vpcie1v8);
648 err = regulator_enable(rockchip->vpcie0v9);
657 regulator_disable(rockchip->vpcie1v8);
659 if (!IS_ERR(rockchip->vpcie3v3))
660 regulator_disable(rockchip->vpcie3v3);
662 if (!IS_ERR(rockchip->vpcie12v))
663 regulator_disable(rockchip->vpcie12v);
668 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
670 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
672 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
675 rockchip_pcie_enable_bw_int(rockchip);
691 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
693 struct device *dev = rockchip->dev;
701 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
702 &intx_domain_ops, rockchip);
704 if (!rockchip->irq_domain) {
712 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
743 rockchip_pcie_write(rockchip, ob_addr_0,
745 rockchip_pcie_write(rockchip, ob_addr_1,
747 rockchip_pcie_write(rockchip, ob_desc_0,
749 rockchip_pcie_write(rockchip, 0,
755 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
776 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
777 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
782 static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip)
784 struct device *dev = rockchip->dev;
785 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
792 rockchip_pcie_cfg_configuration_accesses(rockchip,
800 rockchip->msg_bus_addr = pci_addr;
803 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
814 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
831 err = rockchip_pcie_prog_ob_atu(rockchip,
844 rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1 + offset,
848 rockchip->msg_bus_addr += ((reg_no + offset) << 20);
852 static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip)
858 writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF);
861 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0,
865 dev_err(rockchip->dev, "PCIe link enter L2 timeout!\n");
874 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
878 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) |
880 rockchip_pcie_write(rockchip, (u32)PCIE_CORE_INT, PCIE_CORE_INT_MASK);
882 ret = rockchip_pcie_wait_l2(rockchip);
884 rockchip_pcie_enable_interrupts(rockchip);
888 rockchip_pcie_deinit_phys(rockchip);
890 rockchip_pcie_disable_clocks(rockchip);
892 regulator_disable(rockchip->vpcie0v9);
899 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
902 err = regulator_enable(rockchip->vpcie0v9);
908 err = rockchip_pcie_enable_clocks(rockchip);
912 err = rockchip_pcie_host_init_port(rockchip);
916 err = rockchip_pcie_cfg_atu(rockchip);
921 rockchip_pcie_update_txcredit_mui(rockchip);
922 rockchip_pcie_enable_interrupts(rockchip);
927 rockchip_pcie_deinit_phys(rockchip);
929 rockchip_pcie_disable_clocks(rockchip);
931 regulator_disable(rockchip->vpcie0v9);
937 struct rockchip_pcie *rockchip;
945 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rockchip));
949 rockchip = pci_host_bridge_priv(bridge);
951 platform_set_drvdata(pdev, rockchip);
952 rockchip->dev = dev;
953 rockchip->is_rc = true;
955 err = rockchip_pcie_parse_host_dt(rockchip);
959 err = rockchip_pcie_enable_clocks(rockchip);
963 err = rockchip_pcie_set_vpcie(rockchip);
969 err = rockchip_pcie_host_init_port(rockchip);
973 err = rockchip_pcie_init_irq_domain(rockchip);
977 err = rockchip_pcie_cfg_atu(rockchip);
981 rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M);
982 if (!rockchip->msg_region) {
987 bridge->sysdata = rockchip;
990 err = rockchip_pcie_setup_irq(rockchip);
994 rockchip_pcie_enable_interrupts(rockchip);
1003 irq_domain_remove(rockchip->irq_domain);
1005 rockchip_pcie_deinit_phys(rockchip);
1007 if (!IS_ERR(rockchip->vpcie12v))
1008 regulator_disable(rockchip->vpcie12v);
1009 if (!IS_ERR(rockchip->vpcie3v3))
1010 regulator_disable(rockchip->vpcie3v3);
1011 regulator_disable(rockchip->vpcie1v8);
1012 regulator_disable(rockchip->vpcie0v9);
1014 rockchip_pcie_disable_clocks(rockchip);
1021 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
1022 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
1026 irq_domain_remove(rockchip->irq_domain);
1028 rockchip_pcie_deinit_phys(rockchip);
1030 rockchip_pcie_disable_clocks(rockchip);
1032 if (!IS_ERR(rockchip->vpcie12v))
1033 regulator_disable(rockchip->vpcie12v);
1034 if (!IS_ERR(rockchip->vpcie3v3))
1035 regulator_disable(rockchip->vpcie3v3);
1036 regulator_disable(rockchip->vpcie1v8);
1037 regulator_disable(rockchip->vpcie0v9);
1048 { .compatible = "rockchip,rk3399-pcie", },
1055 .name = "rockchip-pcie",