Lines Matching refs:pcie
7 * arch/sh/drivers/pci/pcie-sh7786.c
33 #include "pcie-rcar.h"
52 struct rcar_pcie pcie;
61 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
64 u32 val = rcar_pci_read_reg(pcie, where & ~3);
74 struct rcar_pcie *pcie = &host->pcie;
102 *data = rcar_pci_read_reg(pcie, PCICONF(index));
104 rcar_pci_write_reg(pcie, *data, PCICONF(index));
110 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
113 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
118 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
120 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
123 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
127 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
132 *data = rcar_pci_read_reg(pcie, PCIECDR);
134 rcar_pci_write_reg(pcie, *data, PCIECDR);
137 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
160 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
180 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
205 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
207 struct device *dev = pcie->dev;
211 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
214 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
219 macsr = rcar_pci_read_reg(pcie, MACSR);
224 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
228 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
232 rcar_pci_write_reg(pcie, macsr, MACSR);
235 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
238 macsr = rcar_pci_read_reg(pcie, MACSR);
241 rcar_pci_write_reg(pcie, macsr, MACSR);
261 struct rcar_pcie *pcie = &host->pcie;
268 rcar_pcie_force_speedup(pcie);
280 rcar_pcie_set_outbound(pcie, i, win);
303 static int phy_wait_for_ack(struct rcar_pcie *pcie)
305 struct device *dev = pcie->dev;
309 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
320 static void phy_write_reg(struct rcar_pcie *pcie,
332 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
333 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
336 phy_wait_for_ack(pcie);
339 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
340 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
343 phy_wait_for_ack(pcie);
346 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
351 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
354 rcar_pci_write_reg(pcie, 1, PCIEMSR);
356 err = rcar_pcie_wait_for_phyrdy(pcie);
365 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
371 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
372 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
375 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
376 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
378 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
382 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
386 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
389 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
392 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
396 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
398 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
401 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
404 err = rcar_pcie_wait_for_dl(pcie);
409 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
418 struct rcar_pcie *pcie = &host->pcie;
421 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
422 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
423 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
424 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
425 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
426 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
427 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
428 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
429 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
430 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
431 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
432 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
434 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
435 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
436 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
443 struct rcar_pcie *pcie = &host->pcie;
449 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
450 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
451 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
452 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
454 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
456 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
457 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
458 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
517 struct rcar_pcie *pcie = &host->pcie;
519 struct device *dev = pcie->dev;
522 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
533 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
547 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
559 struct rcar_pcie *pcie = &host->pcie;
576 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
577 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
591 struct rcar_pcie *pcie = &host->pcie;
630 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
631 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
684 struct rcar_pcie *pcie = &host->pcie;
691 rcar_pci_write_reg(pcie, lower_32_bits(base) | MSIFE, PCIEMSIALR);
692 rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR);
695 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
700 struct rcar_pcie *pcie = &host->pcie;
701 struct device *dev = pcie->dev;
752 struct rcar_pcie *pcie = &host->pcie;
756 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
759 rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
768 struct rcar_pcie *pcie = &host->pcie;
769 struct device *dev = pcie->dev;
773 host->phy = devm_phy_optional_get(dev, "pcie");
781 pcie->base = devm_ioremap_resource(dev, &res);
782 if (IS_ERR(pcie->base))
783 return PTR_ERR(pcie->base);
787 dev_err(dev, "cannot get pcie bus clock\n");
815 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
833 dev_err(pcie->dev, "Failed to map inbound regions!\n");
853 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr,
872 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index);
881 { .compatible = "renesas,pcie-r8a7779",
883 { .compatible = "renesas,pcie-r8a7790",
885 { .compatible = "renesas,pcie-r8a7791",
887 { .compatible = "renesas,pcie-rcar-gen2",
889 { .compatible = "renesas,pcie-r8a7795",
891 { .compatible = "renesas,pcie-rcar-gen3",
900 struct rcar_pcie *pcie;
910 pcie = &host->pcie;
911 pcie->dev = dev;
914 pm_runtime_enable(pcie->dev);
915 err = pm_runtime_get_sync(pcie->dev);
917 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
945 if (rcar_pcie_hw_init(pcie)) {
951 data = rcar_pci_read_reg(pcie, MACSR);
997 struct rcar_pcie *pcie = &host->pcie;
1012 data = rcar_pci_read_reg(pcie, MACSR);
1027 struct rcar_pcie *pcie = &host->pcie;
1029 if (rcar_pci_read_reg(pcie, PMSR) &&
1030 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN))
1034 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
1035 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
1036 return rcar_pcie_wait_for_dl(pcie);
1046 .name = "rcar-pcie",