Lines Matching refs:value
394 static inline void afi_writel(struct tegra_pcie *pcie, u32 value,
397 writel(value, pcie->afi + offset);
405 static inline void pads_writel(struct tegra_pcie *pcie, u32 value,
408 writel(value, pcie->pads + offset);
479 int where, int size, u32 *value)
483 value);
485 return pci_generic_config_read(bus, devfn, where, size, value);
489 int where, int size, u32 value)
493 value);
495 return pci_generic_config_write(bus, devfn, where, size, value);
529 unsigned long value;
535 value = afi_readl(port->pcie, ctrl);
536 value &= ~AFI_PEX_CTRL_RST;
537 afi_writel(port->pcie, value, ctrl);
545 value = afi_readl(port->pcie, ctrl);
546 value |= AFI_PEX_CTRL_RST;
547 afi_writel(port->pcie, value, ctrl);
554 u32 value;
557 value = readl(port->base + RP_VEND_CTL1);
558 value |= RP_VEND_CTL1_ERPT;
559 writel(value, port->base + RP_VEND_CTL1);
562 value = readl(port->base + RP_VEND_XP);
563 value |= RP_VEND_XP_OPPORTUNISTIC_ACK;
564 value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
565 writel(value, port->base + RP_VEND_XP);
571 value = readl(port->base + RP_VEND_XP_BIST);
572 value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE;
573 writel(value, port->base + RP_VEND_XP_BIST);
575 value = readl(port->base + RP_PRIV_MISC);
576 value |= RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE;
577 value |= RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE;
580 value &= ~(RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK |
582 value |= RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD |
586 writel(value, port->base + RP_PRIV_MISC);
592 u32 value;
594 value = readl(port->base + RP_ECTL_2_R1);
595 value &= ~RP_ECTL_2_R1_RX_CTLE_1C_MASK;
596 value |= soc->ectl.regs.rp_ectl_2_r1;
597 writel(value, port->base + RP_ECTL_2_R1);
599 value = readl(port->base + RP_ECTL_4_R1);
600 value &= ~RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK;
601 value |= soc->ectl.regs.rp_ectl_4_r1 <<
603 writel(value, port->base + RP_ECTL_4_R1);
605 value = readl(port->base + RP_ECTL_5_R1);
606 value &= ~RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK;
607 value |= soc->ectl.regs.rp_ectl_5_r1;
608 writel(value, port->base + RP_ECTL_5_R1);
610 value = readl(port->base + RP_ECTL_6_R1);
611 value &= ~RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK;
612 value |= soc->ectl.regs.rp_ectl_6_r1;
613 writel(value, port->base + RP_ECTL_6_R1);
615 value = readl(port->base + RP_ECTL_2_R2);
616 value &= ~RP_ECTL_2_R2_RX_CTLE_1C_MASK;
617 value |= soc->ectl.regs.rp_ectl_2_r2;
618 writel(value, port->base + RP_ECTL_2_R2);
620 value = readl(port->base + RP_ECTL_4_R2);
621 value &= ~RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK;
622 value |= soc->ectl.regs.rp_ectl_4_r2 <<
624 writel(value, port->base + RP_ECTL_4_R2);
626 value = readl(port->base + RP_ECTL_5_R2);
627 value &= ~RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK;
628 value |= soc->ectl.regs.rp_ectl_5_r2;
629 writel(value, port->base + RP_ECTL_5_R2);
631 value = readl(port->base + RP_ECTL_6_R2);
632 value &= ~RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK;
633 value |= soc->ectl.regs.rp_ectl_6_r2;
634 writel(value, port->base + RP_ECTL_6_R2);
640 u32 value;
648 value = readl(port->base + RP_VEND_CTL0);
649 value &= ~RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK;
650 value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH;
651 writel(value, port->base + RP_VEND_CTL0);
655 value = readl(port->base + RP_VEND_XP);
656 value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
657 value |= soc->update_fc_threshold;
658 writel(value, port->base + RP_VEND_XP);
667 value = readl(port->base + RP_LINK_CONTROL_STATUS_2);
668 value &= ~PCI_EXP_LNKSTA_CLS;
669 value |= PCI_EXP_LNKSTA_CLS_2_5GB;
670 writel(value, port->base + RP_LINK_CONTROL_STATUS_2);
677 unsigned long value;
680 value = afi_readl(port->pcie, ctrl);
681 value |= AFI_PEX_CTRL_REFCLK_EN;
684 value |= AFI_PEX_CTRL_CLKREQ_EN;
686 value |= AFI_PEX_CTRL_OVERRIDE_EN;
688 afi_writel(port->pcie, value, ctrl);
693 value = readl(port->base + RP_VEND_CTL2);
694 value |= RP_VEND_CTL2_PCA_ENABLE;
695 writel(value, port->base + RP_VEND_CTL2);
710 unsigned long value;
713 value = afi_readl(port->pcie, ctrl);
714 value &= ~AFI_PEX_CTRL_RST;
715 afi_writel(port->pcie, value, ctrl);
718 value = afi_readl(port->pcie, ctrl);
721 value &= ~AFI_PEX_CTRL_CLKREQ_EN;
723 value &= ~AFI_PEX_CTRL_REFCLK_EN;
724 afi_writel(port->pcie, value, ctrl);
727 value = afi_readl(port->pcie, AFI_PCIE_CONFIG);
728 value |= AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
729 value |= AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index);
730 afi_writel(port->pcie, value, AFI_PCIE_CONFIG);
916 u32 value;
921 value = pads_readl(pcie, soc->pads_pll_ctl);
922 if (value & PADS_PLL_CTL_LOCKDET)
933 u32 value;
940 value = pads_readl(pcie, PADS_CTL);
941 value |= PADS_CTL_IDDQ_1L;
942 pads_writel(pcie, value, PADS_CTL);
948 value = pads_readl(pcie, soc->pads_pll_ctl);
949 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
950 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
951 pads_writel(pcie, value, soc->pads_pll_ctl);
954 value = pads_readl(pcie, soc->pads_pll_ctl);
955 value &= ~PADS_PLL_CTL_RST_B4SM;
956 pads_writel(pcie, value, soc->pads_pll_ctl);
961 value = pads_readl(pcie, soc->pads_pll_ctl);
962 value |= PADS_PLL_CTL_RST_B4SM;
963 pads_writel(pcie, value, soc->pads_pll_ctl);
973 value = pads_readl(pcie, PADS_CTL);
974 value &= ~PADS_CTL_IDDQ_1L;
975 pads_writel(pcie, value, PADS_CTL);
978 value = pads_readl(pcie, PADS_CTL);
979 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
980 pads_writel(pcie, value, PADS_CTL);
988 u32 value;
991 value = pads_readl(pcie, PADS_CTL);
992 value &= ~(PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
993 pads_writel(pcie, value, PADS_CTL);
996 value = pads_readl(pcie, PADS_CTL);
997 value |= PADS_CTL_IDDQ_1L;
998 pads_writel(pcie, value, PADS_CTL);
1001 value = pads_readl(pcie, soc->pads_pll_ctl);
1002 value &= ~PADS_PLL_CTL_RST_B4SM;
1003 pads_writel(pcie, value, soc->pads_pll_ctl);
1111 unsigned long value;
1115 value = afi_readl(pcie, AFI_PLLE_CONTROL);
1116 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
1117 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
1118 afi_writel(pcie, value, AFI_PLLE_CONTROL);
1126 value = afi_readl(pcie, AFI_PCIE_CONFIG);
1127 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
1128 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;
1129 value |= AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO_ALL;
1132 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
1133 value &= ~AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index);
1136 afi_writel(pcie, value, AFI_PCIE_CONFIG);
1139 value = afi_readl(pcie, AFI_FUSE);
1140 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
1141 afi_writel(pcie, value, AFI_FUSE);
1143 value = afi_readl(pcie, AFI_FUSE);
1144 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
1145 afi_writel(pcie, value, AFI_FUSE);
1149 value = afi_readl(pcie, AFI_CONFIGURATION);
1150 value |= AFI_CONFIGURATION_EN_FPCI;
1151 value |= AFI_CONFIGURATION_CLKEN_OVERRIDE;
1152 afi_writel(pcie, value, AFI_CONFIGURATION);
1154 value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
1159 value |= AFI_INTR_EN_PRSNT_SENSE;
1161 afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
1803 u32 value;
1806 value = afi_readl(pcie, AFI_INTR_MASK);
1807 value &= ~AFI_INTR_MASK_MSI_MASK;
1808 afi_writel(pcie, value, AFI_INTR_MASK);
1825 u32 value;
1827 value = afi_readl(pcie, AFI_INTR_MASK);
1828 value &= ~AFI_INTR_MASK_INT_MASK;
1829 afi_writel(pcie, value, AFI_INTR_MASK);
2102 u32 value;
2121 err = of_property_read_u32(port, "nvidia,num-lanes", &value);
2128 if (value > 16) {
2129 dev_err(dev, "invalid # of lanes: %u\n", value);
2134 lanes |= value << (index << 3);
2137 lane += value;
2141 mask |= ((1 << value) - 1) << lane;
2142 lane += value;
2158 rp->lanes = value;
2224 unsigned long value;
2227 value = readl(port->base + RP_PRIV_MISC);
2228 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
2229 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
2230 writel(value, port->base + RP_PRIV_MISC);
2236 value = readl(port->base + RP_VEND_XP);
2238 if (value & RP_VEND_XP_DL_UP)
2252 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2254 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
2272 u32 value;
2281 value = readl(port->base + RP_LINK_CONTROL_STATUS_2);
2282 value &= ~PCI_EXP_LNKSTA_CLS;
2283 value |= PCI_EXP_LNKSTA_CLS_5_0GB;
2284 writel(value, port->base + RP_LINK_CONTROL_STATUS_2);
2293 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2294 if ((value & PCI_EXP_LNKSTA_LT) == 0)
2300 if (value & PCI_EXP_LNKSTA_LT)
2305 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2306 value |= PCI_EXP_LNKCTL_RL;
2307 writel(value, port->base + RP_LINK_CONTROL_STATUS);
2312 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2313 if ((value & PCI_EXP_LNKSTA_LT) == 0)
2319 if (value & PCI_EXP_LNKSTA_LT)
2541 unsigned int value;
2545 value = readl(port->base + RP_VEND_XP);
2547 if (value & RP_VEND_XP_DL_UP)
2550 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2552 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)