Lines Matching refs:pcie
11 * Bits taken from arch/arm/mach-dove/pcie.c
376 struct tegra_pcie *pcie;
394 static inline void afi_writel(struct tegra_pcie *pcie, u32 value,
397 writel(value, pcie->afi + offset);
400 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset)
402 return readl(pcie->afi + offset);
405 static inline void pads_writel(struct tegra_pcie *pcie, u32 value,
408 writel(value, pcie->pads + offset);
411 static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
413 return readl(pcie->pads + offset);
448 struct tegra_pcie *pcie = bus->sysdata;
455 list_for_each_entry(port, &pcie->ports, list) {
469 afi_writel(pcie, base, AFI_FPCI_BAR0);
472 addr = pcie->cfg + (offset & (SZ_4K - 1));
506 const struct tegra_pcie_soc *soc = port->pcie->soc;
535 value = afi_readl(port->pcie, ctrl);
537 afi_writel(port->pcie, value, ctrl);
545 value = afi_readl(port->pcie, ctrl);
547 afi_writel(port->pcie, value, ctrl);
553 const struct tegra_pcie_soc *soc = port->pcie->soc;
591 const struct tegra_pcie_soc *soc = port->pcie->soc;
639 const struct tegra_pcie_soc *soc = port->pcie->soc;
676 const struct tegra_pcie_soc *soc = port->pcie->soc;
680 value = afi_readl(port->pcie, ctrl);
688 afi_writel(port->pcie, value, ctrl);
709 const struct tegra_pcie_soc *soc = port->pcie->soc;
713 value = afi_readl(port->pcie, ctrl);
715 afi_writel(port->pcie, value, ctrl);
718 value = afi_readl(port->pcie, ctrl);
724 afi_writel(port->pcie, value, ctrl);
727 value = afi_readl(port->pcie, AFI_PCIE_CONFIG);
730 afi_writel(port->pcie, value, AFI_PCIE_CONFIG);
735 struct tegra_pcie *pcie = port->pcie;
736 struct device *dev = pcie->dev;
767 struct tegra_pcie *pcie = pdev->bus->sysdata;
774 irq = pcie->irq;
798 struct tegra_pcie *pcie = arg;
799 struct device *dev = pcie->dev;
802 code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
803 signature = afi_readl(pcie, AFI_INTR_SIGNATURE);
804 afi_writel(pcie, 0, AFI_INTR_CODE);
823 u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff;
843 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
847 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
850 size = resource_size(&pcie->cs);
851 afi_writel(pcie, pcie->cs.start, AFI_AXI_BAR0_START);
852 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
865 afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
866 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
867 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
875 afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
876 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
877 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
881 afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
882 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
883 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
890 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
891 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
892 afi_writel(pcie, 0, AFI_FPCI_BAR4);
894 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
895 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
896 afi_writel(pcie, 0, AFI_FPCI_BAR5);
898 if (pcie->soc->has_cache_bars) {
900 afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
901 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
902 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
903 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
907 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
908 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
909 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
910 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
913 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
915 const struct tegra_pcie_soc *soc = pcie->soc;
921 value = pads_readl(pcie, soc->pads_pll_ctl);
929 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
931 struct device *dev = pcie->dev;
932 const struct tegra_pcie_soc *soc = pcie->soc;
937 pads_writel(pcie, 0x0, PADS_CTL_SEL);
940 value = pads_readl(pcie, PADS_CTL);
942 pads_writel(pcie, value, PADS_CTL);
948 value = pads_readl(pcie, soc->pads_pll_ctl);
951 pads_writel(pcie, value, soc->pads_pll_ctl);
954 value = pads_readl(pcie, soc->pads_pll_ctl);
956 pads_writel(pcie, value, soc->pads_pll_ctl);
961 value = pads_readl(pcie, soc->pads_pll_ctl);
963 pads_writel(pcie, value, soc->pads_pll_ctl);
966 err = tegra_pcie_pll_wait(pcie, 500);
973 value = pads_readl(pcie, PADS_CTL);
975 pads_writel(pcie, value, PADS_CTL);
978 value = pads_readl(pcie, PADS_CTL);
980 pads_writel(pcie, value, PADS_CTL);
985 static int tegra_pcie_phy_disable(struct tegra_pcie *pcie)
987 const struct tegra_pcie_soc *soc = pcie->soc;
991 value = pads_readl(pcie, PADS_CTL);
993 pads_writel(pcie, value, PADS_CTL);
996 value = pads_readl(pcie, PADS_CTL);
998 pads_writel(pcie, value, PADS_CTL);
1001 value = pads_readl(pcie, soc->pads_pll_ctl);
1003 pads_writel(pcie, value, soc->pads_pll_ctl);
1012 struct device *dev = port->pcie->dev;
1029 struct device *dev = port->pcie->dev;
1045 static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
1047 struct device *dev = pcie->dev;
1051 if (pcie->legacy_phy) {
1052 if (pcie->phy)
1053 err = phy_power_on(pcie->phy);
1055 err = tegra_pcie_phy_enable(pcie);
1063 list_for_each_entry(port, &pcie->ports, list) {
1076 static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
1078 struct device *dev = pcie->dev;
1082 if (pcie->legacy_phy) {
1083 if (pcie->phy)
1084 err = phy_power_off(pcie->phy);
1086 err = tegra_pcie_phy_disable(pcie);
1094 list_for_each_entry(port, &pcie->ports, list) {
1107 static void tegra_pcie_enable_controller(struct tegra_pcie *pcie)
1109 const struct tegra_pcie_soc *soc = pcie->soc;
1114 if (pcie->phy) {
1115 value = afi_readl(pcie, AFI_PLLE_CONTROL);
1118 afi_writel(pcie, value, AFI_PLLE_CONTROL);
1123 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
1126 value = afi_readl(pcie, AFI_PCIE_CONFIG);
1128 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;
1131 list_for_each_entry(port, &pcie->ports, list) {
1136 afi_writel(pcie, value, AFI_PCIE_CONFIG);
1139 value = afi_readl(pcie, AFI_FUSE);
1141 afi_writel(pcie, value, AFI_FUSE);
1143 value = afi_readl(pcie, AFI_FUSE);
1145 afi_writel(pcie, value, AFI_FUSE);
1149 value = afi_readl(pcie, AFI_CONFIGURATION);
1152 afi_writel(pcie, value, AFI_CONFIGURATION);
1161 afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
1162 afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
1165 afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
1168 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
1171 static void tegra_pcie_power_off(struct tegra_pcie *pcie)
1173 struct device *dev = pcie->dev;
1174 const struct tegra_pcie_soc *soc = pcie->soc;
1177 reset_control_assert(pcie->afi_rst);
1179 clk_disable_unprepare(pcie->pll_e);
1181 clk_disable_unprepare(pcie->cml_clk);
1182 clk_disable_unprepare(pcie->afi_clk);
1187 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
1192 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
1194 struct device *dev = pcie->dev;
1195 const struct tegra_pcie_soc *soc = pcie->soc;
1198 reset_control_assert(pcie->pcie_xrst);
1199 reset_control_assert(pcie->afi_rst);
1200 reset_control_assert(pcie->pex_rst);
1206 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
1223 err = clk_prepare_enable(pcie->afi_clk);
1230 err = clk_prepare_enable(pcie->cml_clk);
1237 err = clk_prepare_enable(pcie->pll_e);
1243 reset_control_deassert(pcie->afi_rst);
1249 clk_disable_unprepare(pcie->cml_clk);
1251 clk_disable_unprepare(pcie->afi_clk);
1256 regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
1261 static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie)
1263 const struct tegra_pcie_soc *soc = pcie->soc;
1266 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
1269 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
1272 static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
1274 struct device *dev = pcie->dev;
1275 const struct tegra_pcie_soc *soc = pcie->soc;
1277 pcie->pex_clk = devm_clk_get(dev, "pex");
1278 if (IS_ERR(pcie->pex_clk))
1279 return PTR_ERR(pcie->pex_clk);
1281 pcie->afi_clk = devm_clk_get(dev, "afi");
1282 if (IS_ERR(pcie->afi_clk))
1283 return PTR_ERR(pcie->afi_clk);
1285 pcie->pll_e = devm_clk_get(dev, "pll_e");
1286 if (IS_ERR(pcie->pll_e))
1287 return PTR_ERR(pcie->pll_e);
1290 pcie->cml_clk = devm_clk_get(dev, "cml");
1291 if (IS_ERR(pcie->cml_clk))
1292 return PTR_ERR(pcie->cml_clk);
1298 static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
1300 struct device *dev = pcie->dev;
1302 pcie->pex_rst = devm_reset_control_get_exclusive(dev, "pex");
1303 if (IS_ERR(pcie->pex_rst))
1304 return PTR_ERR(pcie->pex_rst);
1306 pcie->afi_rst = devm_reset_control_get_exclusive(dev, "afi");
1307 if (IS_ERR(pcie->afi_rst))
1308 return PTR_ERR(pcie->afi_rst);
1310 pcie->pcie_xrst = devm_reset_control_get_exclusive(dev, "pcie_x");
1311 if (IS_ERR(pcie->pcie_xrst))
1312 return PTR_ERR(pcie->pcie_xrst);
1317 static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie)
1319 struct device *dev = pcie->dev;
1322 pcie->phy = devm_phy_optional_get(dev, "pcie");
1323 if (IS_ERR(pcie->phy)) {
1324 err = PTR_ERR(pcie->phy);
1329 err = phy_init(pcie->phy);
1335 pcie->legacy_phy = true;
1363 struct device *dev = port->pcie->dev;
1373 phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i);
1393 static int tegra_pcie_phys_get(struct tegra_pcie *pcie)
1395 const struct tegra_pcie_soc *soc = pcie->soc;
1396 struct device_node *np = pcie->dev->of_node;
1401 return tegra_pcie_phys_get_legacy(pcie);
1403 list_for_each_entry(port, &pcie->ports, list) {
1412 static void tegra_pcie_phys_put(struct tegra_pcie *pcie)
1415 struct device *dev = pcie->dev;
1418 if (pcie->legacy_phy) {
1419 err = phy_exit(pcie->phy);
1425 list_for_each_entry(port, &pcie->ports, list) {
1436 static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
1438 struct device *dev = pcie->dev;
1441 const struct tegra_pcie_soc *soc = pcie->soc;
1444 err = tegra_pcie_clocks_get(pcie);
1450 err = tegra_pcie_resets_get(pcie);
1457 err = tegra_pcie_phys_get(pcie);
1464 pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads");
1465 if (IS_ERR(pcie->pads)) {
1466 err = PTR_ERR(pcie->pads);
1470 pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi");
1471 if (IS_ERR(pcie->afi)) {
1472 err = PTR_ERR(pcie->afi);
1483 pcie->cs = *res;
1486 pcie->cs.end = pcie->cs.start + SZ_4K - 1;
1488 pcie->cfg = devm_ioremap_resource(dev, &pcie->cs);
1489 if (IS_ERR(pcie->cfg)) {
1490 err = PTR_ERR(pcie->cfg);
1499 pcie->irq = err;
1501 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
1511 tegra_pcie_phys_put(pcie);
1515 static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
1517 const struct tegra_pcie_soc *soc = pcie->soc;
1519 if (pcie->irq > 0)
1520 free_irq(pcie->irq, pcie);
1523 tegra_pcie_phys_put(pcie);
1530 struct tegra_pcie *pcie = port->pcie;
1531 const struct tegra_pcie_soc *soc = pcie->soc;
1536 val = afi_readl(pcie, AFI_PCIE_PME);
1538 afi_writel(pcie, val, AFI_PCIE_PME);
1541 err = readl_poll_timeout(pcie->afi + AFI_PCIE_PME, val,
1544 dev_err(pcie->dev, "PME Ack is not received on port: %d\n",
1549 val = afi_readl(pcie, AFI_PCIE_PME);
1551 afi_writel(pcie, val, AFI_PCIE_PME);
1587 struct tegra_pcie *pcie = data;
1588 struct device *dev = pcie->dev;
1589 struct tegra_msi *msi = &pcie->msi;
1593 unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1601 afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4);
1618 reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1690 static int tegra_pcie_msi_setup(struct tegra_pcie *pcie)
1692 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1693 struct platform_device *pdev = to_platform_device(pcie->dev);
1694 struct tegra_msi *msi = &pcie->msi;
1695 struct device *dev = pcie->dev;
1718 tegra_msi_irq_chip.name, pcie);
1748 free_irq(msi->irq, pcie);
1754 static void tegra_pcie_enable_msi(struct tegra_pcie *pcie)
1756 const struct tegra_pcie_soc *soc = pcie->soc;
1757 struct tegra_msi *msi = &pcie->msi;
1760 afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
1761 afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST);
1763 afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
1766 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0);
1767 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1);
1768 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2);
1769 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3);
1770 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4);
1771 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5);
1772 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6);
1773 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7);
1776 reg = afi_readl(pcie, AFI_INTR_MASK);
1778 afi_writel(pcie, reg, AFI_INTR_MASK);
1781 static void tegra_pcie_msi_teardown(struct tegra_pcie *pcie)
1783 struct tegra_msi *msi = &pcie->msi;
1786 dma_free_attrs(pcie->dev, PAGE_SIZE, msi->virt, msi->phys,
1790 free_irq(msi->irq, pcie);
1801 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
1806 value = afi_readl(pcie, AFI_INTR_MASK);
1808 afi_writel(pcie, value, AFI_INTR_MASK);
1811 afi_writel(pcie, 0, AFI_MSI_EN_VEC0);
1812 afi_writel(pcie, 0, AFI_MSI_EN_VEC1);
1813 afi_writel(pcie, 0, AFI_MSI_EN_VEC2);
1814 afi_writel(pcie, 0, AFI_MSI_EN_VEC3);
1815 afi_writel(pcie, 0, AFI_MSI_EN_VEC4);
1816 afi_writel(pcie, 0, AFI_MSI_EN_VEC5);
1817 afi_writel(pcie, 0, AFI_MSI_EN_VEC6);
1818 afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
1823 static void tegra_pcie_disable_interrupts(struct tegra_pcie *pcie)
1827 value = afi_readl(pcie, AFI_INTR_MASK);
1829 afi_writel(pcie, value, AFI_INTR_MASK);
1832 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
1835 struct device *dev = pcie->dev;
1838 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) {
1862 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie") ||
1863 of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
1875 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1892 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1938 static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie)
1940 struct device *dev = pcie->dev;
1943 if (of_device_is_compatible(np, "nvidia,tegra30-pcie"))
1944 pcie->num_supplies = 3;
1945 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie"))
1946 pcie->num_supplies = 2;
1948 if (pcie->num_supplies == 0) {
1953 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
1954 sizeof(*pcie->supplies),
1956 if (!pcie->supplies)
1959 pcie->supplies[0].supply = "pex-clk";
1960 pcie->supplies[1].supply = "vdd";
1962 if (pcie->num_supplies > 2)
1963 pcie->supplies[2].supply = "avdd";
1965 return devm_regulator_bulk_get(dev, pcie->num_supplies, pcie->supplies);
1977 static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
1979 struct device *dev = pcie->dev;
1983 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) {
1984 pcie->num_supplies = 4;
1986 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1987 sizeof(*pcie->supplies),
1989 if (!pcie->supplies)
1992 pcie->supplies[i++].supply = "dvdd-pex";
1993 pcie->supplies[i++].supply = "hvdd-pex-pll";
1994 pcie->supplies[i++].supply = "hvdd-pex";
1995 pcie->supplies[i++].supply = "vddio-pexctl-aud";
1996 } else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
1997 pcie->num_supplies = 3;
1999 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
2000 sizeof(*pcie->supplies),
2002 if (!pcie->supplies)
2005 pcie->supplies[i++].supply = "hvddio-pex";
2006 pcie->supplies[i++].supply = "dvddio-pex";
2007 pcie->supplies[i++].supply = "vddio-pex-ctl";
2008 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
2009 pcie->num_supplies = 4;
2011 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
2012 sizeof(*pcie->supplies),
2014 if (!pcie->supplies)
2017 pcie->supplies[i++].supply = "avddio-pex";
2018 pcie->supplies[i++].supply = "dvddio-pex";
2019 pcie->supplies[i++].supply = "hvdd-pex";
2020 pcie->supplies[i++].supply = "vddio-pex-ctl";
2021 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
2032 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) +
2035 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
2036 sizeof(*pcie->supplies),
2038 if (!pcie->supplies)
2041 pcie->supplies[i++].supply = "avdd-pex-pll";
2042 pcie->supplies[i++].supply = "hvdd-pex";
2043 pcie->supplies[i++].supply = "vddio-pex-ctl";
2044 pcie->supplies[i++].supply = "avdd-plle";
2047 pcie->supplies[i++].supply = "avdd-pexa";
2048 pcie->supplies[i++].supply = "vdd-pexa";
2052 pcie->supplies[i++].supply = "avdd-pexb";
2053 pcie->supplies[i++].supply = "vdd-pexb";
2055 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
2056 pcie->num_supplies = 5;
2058 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
2059 sizeof(*pcie->supplies),
2061 if (!pcie->supplies)
2064 pcie->supplies[0].supply = "avdd-pex";
2065 pcie->supplies[1].supply = "vdd-pex";
2066 pcie->supplies[2].supply = "avdd-pex-pll";
2067 pcie->supplies[3].supply = "avdd-plle";
2068 pcie->supplies[4].supply = "vddio-pex-clk";
2071 if (of_regulator_bulk_available(dev->of_node, pcie->supplies,
2072 pcie->num_supplies))
2073 return devm_regulator_bulk_get(dev, pcie->num_supplies,
2074 pcie->supplies);
2083 devm_kfree(dev, pcie->supplies);
2084 pcie->num_supplies = 0;
2086 return tegra_pcie_get_legacy_regulators(pcie);
2089 static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
2091 struct device *dev = pcie->dev;
2093 const struct tegra_pcie_soc *soc = pcie->soc;
2159 rp->pcie = pcie;
2194 list_add_tail(&rp->list, &pcie->ports);
2197 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
2203 err = tegra_pcie_get_regulators(pcie, mask);
2222 struct device *dev = port->pcie->dev;
2267 static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie)
2269 struct device *dev = pcie->dev;
2274 list_for_each_entry(port, &pcie->ports, list) {
2325 static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
2327 struct device *dev = pcie->dev;
2330 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2338 reset_control_deassert(pcie->pcie_xrst);
2340 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2350 if (pcie->soc->has_gen2)
2351 tegra_pcie_change_link_speed(pcie);
2354 static void tegra_pcie_disable_ports(struct tegra_pcie *pcie)
2358 reset_control_assert(pcie->pcie_xrst);
2360 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
2505 { .compatible = "nvidia,tegra186-pcie", .data = &tegra186_pcie },
2506 { .compatible = "nvidia,tegra210-pcie", .data = &tegra210_pcie },
2507 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie },
2508 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie },
2509 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie },
2516 struct tegra_pcie *pcie = s->private;
2518 if (list_empty(&pcie->ports))
2523 return seq_list_start(&pcie->ports, *pos);
2528 struct tegra_pcie *pcie = s->private;
2530 return seq_list_next(v, &pcie->ports, pos);
2580 static void tegra_pcie_debugfs_exit(struct tegra_pcie *pcie)
2582 debugfs_remove_recursive(pcie->debugfs);
2583 pcie->debugfs = NULL;
2586 static void tegra_pcie_debugfs_init(struct tegra_pcie *pcie)
2588 pcie->debugfs = debugfs_create_dir("pcie", NULL);
2590 debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs, pcie,
2598 struct tegra_pcie *pcie;
2601 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
2605 pcie = pci_host_bridge_priv(host);
2606 host->sysdata = pcie;
2607 platform_set_drvdata(pdev, pcie);
2609 pcie->soc = of_device_get_match_data(dev);
2610 INIT_LIST_HEAD(&pcie->ports);
2611 pcie->dev = dev;
2613 err = tegra_pcie_parse_dt(pcie);
2617 err = tegra_pcie_get_resources(pcie);
2623 err = tegra_pcie_msi_setup(pcie);
2629 pm_runtime_enable(pcie->dev);
2630 err = pm_runtime_get_sync(pcie->dev);
2632 dev_err(dev, "fail to enable pcie controller: %d\n", err);
2646 tegra_pcie_debugfs_init(pcie);
2651 pm_runtime_put_sync(pcie->dev);
2652 pm_runtime_disable(pcie->dev);
2653 tegra_pcie_msi_teardown(pcie);
2655 tegra_pcie_put_resources(pcie);
2661 struct tegra_pcie *pcie = platform_get_drvdata(pdev);
2662 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
2666 tegra_pcie_debugfs_exit(pcie);
2670 pm_runtime_put_sync(pcie->dev);
2671 pm_runtime_disable(pcie->dev);
2674 tegra_pcie_msi_teardown(pcie);
2676 tegra_pcie_put_resources(pcie);
2678 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
2686 struct tegra_pcie *pcie = dev_get_drvdata(dev);
2690 list_for_each_entry(port, &pcie->ports, list)
2693 tegra_pcie_disable_ports(pcie);
2699 tegra_pcie_disable_interrupts(pcie);
2701 if (pcie->soc->program_uphy) {
2702 err = tegra_pcie_phy_power_off(pcie);
2707 reset_control_assert(pcie->pex_rst);
2708 clk_disable_unprepare(pcie->pex_clk);
2711 tegra_pcie_disable_msi(pcie);
2714 tegra_pcie_power_off(pcie);
2721 struct tegra_pcie *pcie = dev_get_drvdata(dev);
2724 err = tegra_pcie_power_on(pcie);
2726 dev_err(dev, "tegra pcie power on fail: %d\n", err);
2736 tegra_pcie_enable_controller(pcie);
2737 tegra_pcie_setup_translations(pcie);
2740 tegra_pcie_enable_msi(pcie);
2742 err = clk_prepare_enable(pcie->pex_clk);
2748 reset_control_deassert(pcie->pex_rst);
2750 if (pcie->soc->program_uphy) {
2751 err = tegra_pcie_phy_power_on(pcie);
2758 tegra_pcie_apply_pad_settings(pcie);
2759 tegra_pcie_enable_ports(pcie);
2764 reset_control_assert(pcie->pex_rst);
2765 clk_disable_unprepare(pcie->pex_clk);
2769 tegra_pcie_power_off(pcie);
2782 .name = "tegra-pcie",