Lines Matching defs:port

271  * entries, one entry per PCIe port. These field definitions and desired
453 struct tegra_pcie_port *port;
455 list_for_each_entry(port, &pcie->ports, list) {
456 if (port->index + 1 == slot) {
457 addr = port->base + (where & ~3);
504 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
506 const struct tegra_pcie_soc *soc = port->pcie->soc;
509 switch (port->index) {
526 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
528 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
532 if (port->reset_gpio) {
533 gpiod_set_value(port->reset_gpio, 1);
535 value = afi_readl(port->pcie, ctrl);
537 afi_writel(port->pcie, value, ctrl);
542 if (port->reset_gpio) {
543 gpiod_set_value(port->reset_gpio, 0);
545 value = afi_readl(port->pcie, ctrl);
547 afi_writel(port->pcie, value, ctrl);
551 static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
553 const struct tegra_pcie_soc *soc = port->pcie->soc;
557 value = readl(port->base + RP_VEND_CTL1);
559 writel(value, port->base + RP_VEND_CTL1);
562 value = readl(port->base + RP_VEND_XP);
565 writel(value, port->base + RP_VEND_XP);
571 value = readl(port->base + RP_VEND_XP_BIST);
573 writel(value, port->base + RP_VEND_XP_BIST);
575 value = readl(port->base + RP_PRIV_MISC);
586 writel(value, port->base + RP_PRIV_MISC);
589 static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)
591 const struct tegra_pcie_soc *soc = port->pcie->soc;
594 value = readl(port->base + RP_ECTL_2_R1);
597 writel(value, port->base + RP_ECTL_2_R1);
599 value = readl(port->base + RP_ECTL_4_R1);
603 writel(value, port->base + RP_ECTL_4_R1);
605 value = readl(port->base + RP_ECTL_5_R1);
608 writel(value, port->base + RP_ECTL_5_R1);
610 value = readl(port->base + RP_ECTL_6_R1);
613 writel(value, port->base + RP_ECTL_6_R1);
615 value = readl(port->base + RP_ECTL_2_R2);
618 writel(value, port->base + RP_ECTL_2_R2);
620 value = readl(port->base + RP_ECTL_4_R2);
624 writel(value, port->base + RP_ECTL_4_R2);
626 value = readl(port->base + RP_ECTL_5_R2);
629 writel(value, port->base + RP_ECTL_5_R2);
631 value = readl(port->base + RP_ECTL_6_R2);
634 writel(value, port->base + RP_ECTL_6_R2);
637 static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
639 const struct tegra_pcie_soc *soc = port->pcie->soc;
648 value = readl(port->base + RP_VEND_CTL0);
651 writel(value, port->base + RP_VEND_CTL0);
655 value = readl(port->base + RP_VEND_XP);
658 writel(value, port->base + RP_VEND_XP);
663 * root port advertises both Gen-1 and Gen-2 speeds in Tegra.
667 value = readl(port->base + RP_LINK_CONTROL_STATUS_2);
670 writel(value, port->base + RP_LINK_CONTROL_STATUS_2);
673 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
675 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
676 const struct tegra_pcie_soc *soc = port->pcie->soc;
680 value = afi_readl(port->pcie, ctrl);
688 afi_writel(port->pcie, value, ctrl);
690 tegra_pcie_port_reset(port);
693 value = readl(port->base + RP_VEND_CTL2);
695 writel(value, port->base + RP_VEND_CTL2);
698 tegra_pcie_enable_rp_features(port);
701 tegra_pcie_program_ectl_settings(port);
703 tegra_pcie_apply_sw_fixup(port);
706 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
708 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
709 const struct tegra_pcie_soc *soc = port->pcie->soc;
712 /* assert port reset */
713 value = afi_readl(port->pcie, ctrl);
715 afi_writel(port->pcie, value, ctrl);
718 value = afi_readl(port->pcie, ctrl);
724 afi_writel(port->pcie, value, ctrl);
726 /* disable PCIe port and set CLKREQ# as GPIO to allow PLLE power down */
727 value = afi_readl(port->pcie, AFI_PCIE_CONFIG);
728 value |= AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
729 value |= AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index);
730 afi_writel(port->pcie, value, AFI_PCIE_CONFIG);
733 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
735 struct tegra_pcie *pcie = port->pcie;
738 devm_iounmap(dev, port->base);
739 devm_release_mem_region(dev, port->regs.start,
740 resource_size(&port->regs));
741 list_del(&port->list);
742 devm_kfree(dev, port);
1010 static int tegra_pcie_port_phy_power_on(struct tegra_pcie_port *port)
1012 struct device *dev = port->pcie->dev;
1016 for (i = 0; i < port->lanes; i++) {
1017 err = phy_power_on(port->phys[i]);
1027 static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
1029 struct device *dev = port->pcie->dev;
1033 for (i = 0; i < port->lanes; i++) {
1034 err = phy_power_off(port->phys[i]);
1048 struct tegra_pcie_port *port;
1063 list_for_each_entry(port, &pcie->ports, list) {
1064 err = tegra_pcie_port_phy_power_on(port);
1067 "failed to power on PCIe port %u PHY: %d\n",
1068 port->index, err);
1079 struct tegra_pcie_port *port;
1094 list_for_each_entry(port, &pcie->ports, list) {
1095 err = tegra_pcie_port_phy_power_off(port);
1098 "failed to power off PCIe port %u PHY: %d\n",
1099 port->index, err);
1110 struct tegra_pcie_port *port;
1131 list_for_each_entry(port, &pcie->ports, list) {
1132 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
1133 value &= ~AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index);
1361 static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port)
1363 struct device *dev = port->pcie->dev;
1368 port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL);
1369 if (!port->phys)
1372 for (i = 0; i < port->lanes; i++) {
1373 phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i);
1387 port->phys[i] = phy;
1397 struct tegra_pcie_port *port;
1403 list_for_each_entry(port, &pcie->ports, list) {
1404 err = tegra_pcie_port_get_phys(port);
1414 struct tegra_pcie_port *port;
1425 list_for_each_entry(port, &pcie->ports, list) {
1426 for (i = 0; i < port->lanes; i++) {
1427 err = phy_exit(port->phys[i]);
1528 static void tegra_pcie_pme_turnoff(struct tegra_pcie_port *port)
1530 struct tegra_pcie *pcie = port->pcie;
1537 val |= (0x1 << soc->ports[port->index].pme.turnoff_bit);
1540 ack_bit = soc->ports[port->index].pme.ack_bit;
1544 dev_err(pcie->dev, "PME Ack is not received on port: %d\n",
1545 port->index);
1550 val &= ~(0x1 << soc->ports[port->index].pme.turnoff_bit);
2092 struct device_node *np = dev->of_node, *port;
2099 for_each_child_of_node(np, port) {
2105 err = of_pci_get_devfn(port);
2114 dev_err(dev, "invalid port number: %d\n", index);
2121 err = of_property_read_u32(port, "nvidia,num-lanes", &value);
2136 if (!of_device_is_available(port)) {
2150 err = of_address_to_resource(port, 0, &rp->regs);
2160 rp->np = port;
2176 * and in this case fall back to using AFI per port register
2179 rp->reset_gpio = devm_gpiod_get_from_of_node(dev, port,
2210 of_node_put(port);
2220 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
2222 struct device *dev = port->pcie->dev;
2227 value = readl(port->base + RP_PRIV_MISC);
2230 writel(value, port->base + RP_PRIV_MISC);
2236 value = readl(port->base + RP_VEND_XP);
2245 dev_dbg(dev, "link %u down, retrying\n", port->index);
2252 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2261 tegra_pcie_port_reset(port);
2270 struct tegra_pcie_port *port;
2274 list_for_each_entry(port, &pcie->ports, list) {
2281 value = readl(port->base + RP_LINK_CONTROL_STATUS_2);
2284 writel(value, port->base + RP_LINK_CONTROL_STATUS_2);
2293 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2301 dev_warn(dev, "PCIe port %u link is in recovery\n",
2302 port->index);
2305 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2307 writel(value, port->base + RP_LINK_CONTROL_STATUS);
2312 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2320 dev_err(dev, "failed to retrain link of port %u\n",
2321 port->index);
2328 struct tegra_pcie_port *port, *tmp;
2330 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2331 dev_info(dev, "probing port %u, using %u lanes\n",
2332 port->index, port->lanes);
2334 tegra_pcie_port_enable(port);
2340 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2341 if (tegra_pcie_port_check_link(port))
2344 dev_info(dev, "link %u down, ignoring\n", port->index);
2346 tegra_pcie_port_disable(port);
2347 tegra_pcie_port_free(port);
2356 struct tegra_pcie_port *port, *tmp;
2360 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
2361 tegra_pcie_port_disable(port);
2540 struct tegra_pcie_port *port;
2543 port = list_entry(v, struct tegra_pcie_port, list);
2545 value = readl(port->base + RP_VEND_XP);
2550 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2555 seq_printf(s, "%2u ", port->index);
2663 struct tegra_pcie_port *port, *tmp;
2678 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
2679 tegra_pcie_port_free(port);
2687 struct tegra_pcie_port *port;
2690 list_for_each_entry(port, &pcie->ports, list)
2691 tegra_pcie_pme_turnoff(port);