Lines Matching refs:mvebu_writel
108 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
135 mvebu_writel(port, stat, PCIE_STAT_OFF);
145 mvebu_writel(port, stat, PCIE_STAT_OFF);
165 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
166 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
167 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
171 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
172 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
173 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
176 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
177 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
178 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
185 mvebu_writel(port, cs->base & 0xffff0000,
187 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
188 mvebu_writel(port,
202 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
203 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
204 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
210 mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0));
211 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0));
226 mvebu_writel(port, cmd, PCIE_CMD_OFF);
231 mvebu_writel(port, mask, PCIE_MASK_OFF);
240 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
264 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
542 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
554 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
558 mvebu_writel(port, new, PCIE_RC_RTSTA);
806 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);