Lines Matching refs:base
80 phys_addr_t base;
88 void __iomem *base;
110 writel(val, port->base + reg);
115 return readl(port->base + reg);
185 mvebu_writel(port, cs->base & 0xffff0000,
202 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
238 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
262 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
289 phys_addr_t base, size_t size)
294 mvebu_mbus_del_window(base, sz);
295 base += sz;
308 phys_addr_t base, size_t size,
317 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
320 phys_addr_t end = base + sz - 1;
324 &base, &end, ret);
325 mvebu_pcie_del_windows(port, base - size_mapped,
332 base += sz;
343 if (desired->base == cur->base && desired->remap == cur->remap &&
348 mvebu_pcie_del_windows(port, cur->base, cur->size);
350 cur->base = 0;
362 mvebu_pcie_add_windows(port, target, attribute, desired->base,
389 * calculate the base address and size of the address decoding
396 desired.base = port->pcie->io.start + desired.remap;
421 * calculate the base address and size of the address decoding
425 desired.base = ((conf->membase & 0xFFF0) << 16);
427 desired.base + 1;
704 * base address aligned on their size, and their size must be
1115 port->base = mvebu_pcie_map_registers(pdev, child, port);
1116 if (IS_ERR(port->base)) {
1118 port->base = NULL;