Lines Matching refs:value
413 * Set maximal link speed value also into PCIe Link Control 2 register.
414 * Armada 3700 Functional Specification says that default value is based
415 * on SPEED_GEN but tests showed that default value is always 8.0 GT/s.
513 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
515 * id in high 16 bits. Updating this register changes readback value of
517 * for erratum 4.1: "The value of device and vendor ID is incorrect".
524 * because the default value is Mass storage controller (0x010400).
665 * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only
667 * a read value of 0xFFFFFFFF.
668 * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7)
670 * with a read value of 0xFFFF0001.
671 * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means
701 * read-data value of 0001h for the Vendor ID field and
776 int reg, u32 *value)
782 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
797 *value = val;
835 int reg, u32 *value)
842 *value = PCI_EXP_SLTSTA_PDS << 16;
847 *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE;
848 *value |= le16_to_cpu(bridge->pcie_conf.rootctl) & PCI_EXP_RTCTL_CRSSVE;
849 *value |= PCI_EXP_RTCAP_CRSVIS << 16;
856 *value = msglog >> 16;
858 *value |= PCI_EXP_RTSTA_PME;
870 *value = val;
882 *value = val;
888 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);