Lines Matching defs:val
104 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
105 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
111 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
299 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
301 writel(val, pcie->base + reg);
311 u32 val;
314 val = advk_readl(pcie, CFG_REG);
315 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
648 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val)
683 if (val)
684 *val = advk_readl(pcie, PIO_RD_DATA);
694 if (allow_crs && val) {
707 *val = CFG_RD_CRS_VAL;
792 u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);
794 val |= PCI_BRIDGE_CTL_BUS_RESET << 16;
796 val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16);
797 *value = val;
819 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);
821 val |= HOT_RESET_GEN;
823 val &= ~HOT_RESET_GEN;
824 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG);
846 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
847 *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE;
863 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
869 val |= PCI_EXP_LNKCAP_DLLLARC;
870 *value = val;
876 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &
879 val |= (PCI_EXP_LNKSTA_LT << 16);
881 val |= (PCI_EXP_LNKSTA_DLLLA << 16);
882 *value = val;
915 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &
918 val |= PCIE_MSG_PM_PME_MASK;
919 advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
1025 int where, int size, u32 *val)
1034 *val = 0xffffffff;
1040 size, val);
1084 ret = advk_pcie_check_pio_status(pcie, allow_crs, val);
1091 *val = (*val >> (8 * (where & 3))) & 0xff;
1093 *val = (*val >> (8 * (where & 3))) & 0xffff;
1103 *val = CFG_RD_CRS_VAL;
1108 *val = 0xffffffff;
1113 int where, int size, u32 val)
1127 size, val);
1151 reg = val << (8 * offset);