Lines Matching refs:pcie
28 #include "pcie-mobiveil.h"
53 struct mobiveil_pcie *pcie = bus->sysdata;
54 struct mobiveil_root_port *rp = &pcie->rp;
62 return pcie->csr_axi_slave_base + where;
74 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
88 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
89 struct device *dev = &pcie->pdev->dev;
90 struct mobiveil_root_port *rp = &pcie->rp;
105 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
106 mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
111 shifted_status = mobiveil_csr_readl(pcie,
126 mobiveil_csr_writel(pcie,
131 shifted_status = mobiveil_csr_readl(pcie,
139 msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
143 msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
151 msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
153 msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
162 msi_status = readl_relaxed(pcie->apb_csr_base +
167 mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
171 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
173 struct device *dev = &pcie->pdev->dev;
174 struct platform_device *pdev = pcie->pdev;
176 struct mobiveil_root_port *rp = &pcie->rp;
190 pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
191 if (IS_ERR(pcie->csr_axi_slave_base))
192 return PTR_ERR(pcie->csr_axi_slave_base);
193 pcie->pcie_reg_base = res->start;
196 if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
197 pcie->apio_wins = MAX_PIO_WINDOWS;
199 if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
200 pcie->ppio_wins = MAX_PIO_WINDOWS;
205 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
207 phys_addr_t msg_addr = pcie->pcie_reg_base;
208 struct mobiveil_msi *msi = &pcie->rp.msi;
214 pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
216 pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
217 writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
218 writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
221 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
223 struct mobiveil_root_port *rp = &pcie->rp;
228 pcie->ib_wins_configured = 0;
229 pcie->ob_wins_configured = 0;
233 value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);
236 mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);
243 value = mobiveil_csr_readl(pcie, PCI_COMMAND);
245 mobiveil_csr_writel(pcie, value, PCI_COMMAND);
251 pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL);
253 mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL);
259 value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL);
261 mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
264 value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL);
266 mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
276 program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0,
280 program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
292 program_ob_windows(pcie, pcie->ob_wins_configured,
299 value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
302 mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
310 struct mobiveil_pcie *pcie;
315 pcie = irq_desc_get_chip_data(desc);
316 rp = &pcie->rp;
319 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
321 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
328 struct mobiveil_pcie *pcie;
333 pcie = irq_desc_get_chip_data(desc);
334 rp = &pcie->rp;
337 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
339 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
380 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
381 phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
387 dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
407 struct mobiveil_pcie *pcie = domain->host_data;
408 struct mobiveil_msi *msi = &pcie->rp.msi;
434 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
435 struct mobiveil_msi *msi = &pcie->rp.msi;
440 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
452 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
454 struct device *dev = &pcie->pdev->dev;
456 struct mobiveil_msi *msi = &pcie->rp.msi;
460 &msi_domain_ops, pcie);
478 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
480 struct device *dev = &pcie->pdev->dev;
482 struct mobiveil_root_port *rp = &pcie->rp;
486 &intx_domain_ops, pcie);
496 return mobiveil_allocate_msi_domains(pcie);
499 static int mobiveil_pcie_integrated_interrupt_init(struct mobiveil_pcie *pcie)
501 struct platform_device *pdev = pcie->pdev;
503 struct mobiveil_root_port *rp = &pcie->rp;
509 pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
510 if (IS_ERR(pcie->apb_csr_base))
511 return PTR_ERR(pcie->apb_csr_base);
514 mobiveil_pcie_enable_msi(pcie);
521 ret = mobiveil_pcie_init_irq_domain(pcie);
527 irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie);
530 mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
537 static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie)
539 struct mobiveil_root_port *rp = &pcie->rp;
542 return rp->ops->interrupt_init(pcie);
544 return mobiveil_pcie_integrated_interrupt_init(pcie);
547 static bool mobiveil_pcie_is_bridge(struct mobiveil_pcie *pcie)
551 header_type = mobiveil_csr_readb(pcie, PCI_HEADER_TYPE);
557 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
559 struct mobiveil_root_port *rp = &pcie->rp;
561 struct device *dev = &pcie->pdev->dev;
564 ret = mobiveil_pcie_parse_dt(pcie);
570 if (!mobiveil_pcie_is_bridge(pcie))
577 ret = mobiveil_host_init(pcie, false);
583 ret = mobiveil_pcie_interrupt_init(pcie);
590 bridge->sysdata = pcie;
593 ret = mobiveil_bringup_link(pcie);