Lines Matching refs:val
78 u32 val;
80 val = readl(priv->base + PCL_APP_READY_CTRL);
82 val |= PCL_APP_LTSSM_ENABLE;
84 val &= ~PCL_APP_LTSSM_ENABLE;
85 writel(val, priv->base + PCL_APP_READY_CTRL);
90 u32 val;
93 val = readl(priv->base + PCL_MODE);
94 val |= PCL_MODE_REGEN;
95 val &= ~PCL_MODE_REGVAL;
96 writel(val, priv->base + PCL_MODE);
99 val = readl(priv->base + PCL_APP_PM0);
100 val |= PCL_SYS_AUX_PWR_DET;
101 writel(val, priv->base + PCL_APP_PM0);
104 val = readl(priv->base + PCL_PINCTRL0);
105 val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
107 val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
109 writel(val, priv->base + PCL_PINCTRL0);
116 val = readl(priv->base + PCL_PINCTRL0);
117 val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
118 writel(val, priv->base + PCL_PINCTRL0);
141 u32 val, mask;
143 val = readl(priv->base + PCL_STATUS_LINK);
146 return (val & mask) == mask;
180 u32 val;
184 val = readl(priv->base + PCL_RCV_INTX);
185 val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
186 writel(val, priv->base + PCL_RCV_INTX);
197 u32 val;
201 val = readl(priv->base + PCL_RCV_INTX);
202 val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
203 writel(val, priv->base + PCL_RCV_INTX);
235 u32 val, bit, virq;
238 val = readl(priv->base + PCL_RCV_INT);
240 if (val & PCL_CFG_BW_MGT_STATUS)
242 if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
244 if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
246 if (val & PCL_CFG_PME_MSI_STATUS)
249 writel(val, priv->base + PCL_RCV_INT);
254 val = readl(priv->base + PCL_RCV_INTX);
255 reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);