Lines Matching refs:pcie
34 #include "pcie-designware.h"
321 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value,
324 writel_relaxed(value, pcie->appl_base + reg);
327 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg)
329 return readl_relaxed(pcie->appl_base + reg);
339 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
348 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
351 if (pcie->init_link_width > current_link_width) {
353 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
357 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
360 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
363 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
371 struct tegra_pcie_dw *pcie = arg;
372 struct dw_pcie *pci = &pcie->pci;
377 status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
379 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
380 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
383 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
385 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
387 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
389 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
398 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
400 appl_writel(pcie,
406 appl_writel(pcie,
410 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
418 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
440 static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie)
444 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
445 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
446 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
447 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
448 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
449 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
450 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
451 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
452 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
453 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
454 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
455 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
456 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
457 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
458 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
459 appl_writel(pcie, 0xFFFFFFFF, APPL_MSI_CTRL_2);
461 val = appl_readl(pcie, APPL_CTRL);
463 appl_writel(pcie, val, APPL_CTRL);
468 struct tegra_pcie_dw *pcie = arg;
469 struct dw_pcie *pci = &pcie->pci;
472 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
478 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
481 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
493 appl_writel(pcie, val, APPL_LTR_MSG_1);
496 val = appl_readl(pcie, APPL_LTR_MSG_2);
498 appl_writel(pcie, val, APPL_LTR_MSG_2);
502 val = appl_readl(pcie, APPL_LTR_MSG_2);
510 dev_err(pcie->dev, "Failed to send LTR message\n");
518 struct tegra_pcie_dw *pcie = arg;
519 struct dw_pcie_ep *ep = &pcie->pci.ep;
523 status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
525 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
526 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
529 pex_ep_event_hot_rst_done(pcie);
532 link_status = appl_readl(pcie, APPL_LINK_STATUS);
534 dev_dbg(pcie->dev, "Link is up with Host\n");
543 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
544 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_15);
553 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
555 appl_writel(pcie, status_l0, APPL_INTR_STATUS_L0);
600 static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
604 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
606 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
609 static void disable_aspm_l12(struct tegra_pcie_dw *pcie)
613 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
615 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
618 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
622 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]);
627 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
628 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]);
635 struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *)
640 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S));
643 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S));
646 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1));
649 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1));
652 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2));
655 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid],
661 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
666 static void init_host_aspm(struct tegra_pcie_dw *pcie)
668 struct dw_pcie *pci = &pcie->pci;
672 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP;
677 dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val);
680 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
682 val |= (pcie->aspm_cmrt << 8);
683 val |= (pcie->aspm_pwr_on_t << 19);
684 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
689 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
694 static void init_debugfs(struct tegra_pcie_dw *pcie)
696 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs,
700 static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; }
701 static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; }
702 static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; }
703 static inline void init_debugfs(struct tegra_pcie_dw *pcie) { return; }
709 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
713 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
715 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
717 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
719 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
721 if (pcie->enable_cdm_check) {
722 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
724 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
726 val = appl_readl(pcie, APPL_INTR_EN_L1_18);
729 appl_writel(pcie, val, APPL_INTR_EN_L1_18);
732 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
734 pcie->init_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w);
736 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
739 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL,
746 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
750 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
753 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
755 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
761 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
767 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
773 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
776 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
782 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
785 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
786 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
787 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
788 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
789 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
790 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
791 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
792 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
793 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
794 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
795 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
796 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
797 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
798 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
799 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
807 static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
809 struct dw_pcie *pci = &pcie->pci;
813 for (i = 0; i < pcie->num_lanes; i++) {
863 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
885 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
887 val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, pcie->num_lanes);
888 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
890 config_gen3_gen4_eq_presets(pcie);
892 init_host_aspm(pcie);
898 if (pcie->update_fc_fixup) {
906 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
909 val = appl_readl(pcie, APPL_PINMUX);
911 appl_writel(pcie, val, APPL_PINMUX);
916 val = appl_readl(pcie, APPL_CTRL);
918 appl_writel(pcie, val, APPL_CTRL);
921 val = appl_readl(pcie, APPL_PINMUX);
923 appl_writel(pcie, val, APPL_PINMUX);
931 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
947 val = appl_readl(pcie, APPL_DEBUG);
950 tmp = appl_readl(pcie, APPL_LINK_STATUS);
960 val = appl_readl(pcie, APPL_CTRL);
962 appl_writel(pcie, val, APPL_CTRL);
964 reset_control_assert(pcie->core_rst);
965 reset_control_deassert(pcie->core_rst);
978 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
984 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
993 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
994 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
1006 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1008 enable_irq(pcie->pex_rst_irq);
1015 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1017 disable_irq(pcie->pex_rst_irq);
1031 static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie)
1033 unsigned int phy_count = pcie->phy_count;
1036 phy_power_off(pcie->phys[phy_count]);
1037 phy_exit(pcie->phys[phy_count]);
1041 static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
1046 for (i = 0; i < pcie->phy_count; i++) {
1047 ret = phy_init(pcie->phys[i]);
1051 ret = phy_power_on(pcie->phys[i]);
1060 phy_power_off(pcie->phys[i]);
1062 phy_exit(pcie->phys[i]);
1068 static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
1070 struct device_node *np = pcie->dev->of_node;
1073 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt);
1075 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);
1080 &pcie->aspm_pwr_on_t);
1082 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n",
1086 &pcie->aspm_l0s_enter_lat);
1088 dev_info(pcie->dev,
1091 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
1093 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
1097 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid);
1099 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret);
1105 dev_err(pcie->dev, "Failed to find PHY entries: %d\n",
1109 pcie->phy_count = ret;
1112 pcie->update_fc_fixup = true;
1114 pcie->supports_clkreq =
1115 of_property_read_bool(pcie->dev->of_node, "supports-clkreq");
1117 pcie->enable_cdm_check =
1120 if (pcie->mode == DW_PCIE_RC_TYPE)
1124 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN);
1125 if (IS_ERR(pcie->pex_rst_gpiod)) {
1126 int err = PTR_ERR(pcie->pex_rst_gpiod);
1132 dev_printk(level, pcie->dev,
1138 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev,
1141 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) {
1142 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod);
1148 dev_printk(level, pcie->dev,
1151 pcie->pex_refclk_sel_gpiod = NULL;
1157 static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
1165 if (pcie->cid == 5)
1172 req.controller_state.pcie_controller = pcie->cid;
1182 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1185 static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
1197 req.ep_ctrlr_pll_init.ep_controller = pcie->cid;
1200 req.ep_ctrlr_pll_off.ep_controller = pcie->cid;
1210 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1213 static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
1215 struct pcie_port *pp = &pcie->pci.pp;
1237 dev_err(pcie->dev, "Failed to find downstream devices\n");
1244 dev_err(pcie->dev,
1251 static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
1253 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
1254 if (IS_ERR(pcie->slot_ctl_3v3)) {
1255 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV)
1256 return PTR_ERR(pcie->slot_ctl_3v3);
1258 pcie->slot_ctl_3v3 = NULL;
1261 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v");
1262 if (IS_ERR(pcie->slot_ctl_12v)) {
1263 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV)
1264 return PTR_ERR(pcie->slot_ctl_12v);
1266 pcie->slot_ctl_12v = NULL;
1272 static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
1276 if (pcie->slot_ctl_3v3) {
1277 ret = regulator_enable(pcie->slot_ctl_3v3);
1279 dev_err(pcie->dev,
1285 if (pcie->slot_ctl_12v) {
1286 ret = regulator_enable(pcie->slot_ctl_12v);
1288 dev_err(pcie->dev,
1299 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v)
1305 if (pcie->slot_ctl_3v3)
1306 regulator_disable(pcie->slot_ctl_3v3);
1310 static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie)
1312 if (pcie->slot_ctl_12v)
1313 regulator_disable(pcie->slot_ctl_12v);
1314 if (pcie->slot_ctl_3v3)
1315 regulator_disable(pcie->slot_ctl_3v3);
1318 static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
1324 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
1326 dev_err(pcie->dev,
1327 "Failed to enable controller %u: %d\n", pcie->cid, ret);
1331 ret = tegra_pcie_enable_slot_regulators(pcie);
1335 ret = regulator_enable(pcie->pex_ctl_supply);
1337 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
1341 ret = clk_prepare_enable(pcie->core_clk);
1343 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret);
1347 ret = reset_control_deassert(pcie->core_apb_rst);
1349 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n",
1356 val = appl_readl(pcie, APPL_CTRL);
1360 appl_writel(pcie, val, APPL_CTRL);
1363 ret = tegra_pcie_enable_phy(pcie);
1365 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret);
1370 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1374 appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE);
1376 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1378 val = appl_readl(pcie, APPL_CTRL);
1379 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);
1381 val = appl_readl(pcie, APPL_CFG_MISC);
1383 appl_writel(pcie, val, APPL_CFG_MISC);
1385 if (!pcie->supports_clkreq) {
1386 val = appl_readl(pcie, APPL_PINMUX);
1389 appl_writel(pcie, val, APPL_PINMUX);
1393 appl_writel(pcie,
1394 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK,
1397 reset_control_deassert(pcie->core_rst);
1399 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
1403 if (!pcie->supports_clkreq) {
1404 disable_aspm_l11(pcie);
1405 disable_aspm_l12(pcie);
1411 reset_control_assert(pcie->core_apb_rst);
1413 clk_disable_unprepare(pcie->core_clk);
1415 regulator_disable(pcie->pex_ctl_supply);
1417 tegra_pcie_disable_slot_regulators(pcie);
1419 tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1424 static int __deinit_controller(struct tegra_pcie_dw *pcie)
1428 ret = reset_control_assert(pcie->core_rst);
1430 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n",
1435 tegra_pcie_disable_phy(pcie);
1437 ret = reset_control_assert(pcie->core_apb_rst);
1439 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret);
1443 clk_disable_unprepare(pcie->core_clk);
1445 ret = regulator_disable(pcie->pex_ctl_supply);
1447 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret);
1451 tegra_pcie_disable_slot_regulators(pcie);
1453 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1455 dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
1456 pcie->cid, ret);
1463 static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
1465 struct dw_pcie *pci = &pcie->pci;
1469 ret = tegra_pcie_config_controller(pcie, false);
1477 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret);
1484 return __deinit_controller(pcie);
1487 static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)
1491 if (!tegra_pcie_dw_link_up(&pcie->pci))
1494 val = appl_readl(pcie, APPL_RADM_STATUS);
1496 appl_writel(pcie, val, APPL_RADM_STATUS);
1498 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,
1503 static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
1508 if (!tegra_pcie_dw_link_up(&pcie->pci)) {
1509 dev_dbg(pcie->dev, "PCIe link is not up...!\n");
1513 if (tegra_pcie_try_link_l2(pcie)) {
1514 dev_info(pcie->dev, "Link didn't transition to L2 state\n");
1521 data = appl_readl(pcie, APPL_PINMUX);
1523 appl_writel(pcie, data, APPL_PINMUX);
1525 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
1533 dev_info(pcie->dev, "Link didn't go to detect state\n");
1536 data = appl_readl(pcie, APPL_CTRL);
1538 appl_writel(pcie, data, APPL_CTRL);
1545 data = appl_readl(pcie, APPL_PINMUX);
1550 appl_writel(pcie, data, APPL_PINMUX);
1553 static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
1555 tegra_pcie_downstream_dev_to_D0(pcie);
1556 dw_pcie_host_deinit(&pcie->pci.pp);
1557 tegra_pcie_dw_pme_turnoff(pcie);
1559 return __deinit_controller(pcie);
1562 static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
1564 struct pcie_port *pp = &pcie->pci.pp;
1565 struct device *dev = pcie->dev;
1592 tegra_pcie_init_controller(pcie);
1594 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci);
1595 if (!pcie->link_state) {
1606 pcie->debugfs = debugfs_create_dir(name, NULL);
1607 init_debugfs(pcie);
1612 tegra_pcie_deinit_controller(pcie);
1619 static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
1624 if (pcie->ep_state == EP_STATE_DISABLED)
1628 val = appl_readl(pcie, APPL_CTRL);
1630 appl_writel(pcie, val, APPL_CTRL);
1632 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
1638 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
1640 reset_control_assert(pcie->core_rst);
1642 tegra_pcie_disable_phy(pcie);
1644 reset_control_assert(pcie->core_apb_rst);
1646 clk_disable_unprepare(pcie->core_clk);
1648 pm_runtime_put_sync(pcie->dev);
1650 ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
1652 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret);
1654 pcie->ep_state = EP_STATE_DISABLED;
1655 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n");
1658 static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
1660 struct dw_pcie *pci = &pcie->pci;
1662 struct device *dev = pcie->dev;
1666 if (pcie->ep_state == EP_STATE_ENABLED)
1676 ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
1682 ret = clk_prepare_enable(pcie->core_clk);
1688 ret = reset_control_deassert(pcie->core_apb_rst);
1694 ret = tegra_pcie_enable_phy(pcie);
1701 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
1702 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
1703 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
1704 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
1705 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
1706 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
1707 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
1708 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
1709 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
1710 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
1711 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
1712 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
1713 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
1714 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
1715 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
1718 val = appl_readl(pcie, APPL_DM_TYPE);
1721 appl_writel(pcie, val, APPL_DM_TYPE);
1723 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1725 val = appl_readl(pcie, APPL_CTRL);
1728 appl_writel(pcie, val, APPL_CTRL);
1730 val = appl_readl(pcie, APPL_CFG_MISC);
1733 appl_writel(pcie, val, APPL_CFG_MISC);
1735 val = appl_readl(pcie, APPL_PINMUX);
1738 appl_writel(pcie, val, APPL_PINMUX);
1740 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1743 appl_writel(pcie, pcie->atu_dma_res->start &
1747 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
1751 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
1753 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
1756 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
1758 reset_control_deassert(pcie->core_rst);
1760 if (pcie->update_fc_fixup) {
1766 config_gen3_gen4_eq_presets(pcie);
1768 init_host_aspm(pcie);
1771 if (!pcie->supports_clkreq) {
1772 disable_aspm_l11(pcie);
1773 disable_aspm_l12(pcie);
1780 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
1782 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
1799 val = appl_readl(pcie, APPL_CTRL);
1801 appl_writel(pcie, val, APPL_CTRL);
1803 pcie->ep_state = EP_STATE_ENABLED;
1809 reset_control_assert(pcie->core_rst);
1810 tegra_pcie_disable_phy(pcie);
1812 reset_control_assert(pcie->core_apb_rst);
1814 clk_disable_unprepare(pcie->core_clk);
1816 tegra_pcie_bpmp_set_pll_state(pcie, false);
1823 struct tegra_pcie_dw *pcie = arg;
1825 if (gpiod_get_value(pcie->pex_rst_gpiod))
1826 pex_ep_event_pex_rst_assert(pcie);
1828 pex_ep_event_pex_rst_deassert(pcie);
1833 static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq)
1839 appl_writel(pcie, 1, APPL_LEGACY_INTX);
1841 appl_writel(pcie, 0, APPL_LEGACY_INTX);
1845 static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)
1850 appl_writel(pcie, BIT(irq), APPL_MSI_CTRL_1);
1855 static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq)
1857 struct dw_pcie_ep *ep = &pcie->pci.ep;
1869 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1873 return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
1876 return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num);
1879 return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num);
1910 static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
1913 struct dw_pcie *pci = &pcie->pci;
1914 struct device *dev = pcie->dev;
1931 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME);
1938 ret = gpiod_to_irq(pcie->pex_rst_gpiod);
1943 pcie->pex_rst_irq = (unsigned int)ret;
1946 pcie->cid);
1952 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN);
1954 pcie->ep_state = EP_STATE_DISABLED;
1956 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL,
1960 name, (void *)pcie);
1967 pcie->cid);
1991 struct tegra_pcie_dw *pcie;
2002 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
2003 if (!pcie)
2006 pci = &pcie->pci;
2013 pcie->dev = &pdev->dev;
2014 pcie->mode = (enum dw_pcie_device_mode)data->mode;
2016 ret = tegra_pcie_dw_parse_dt(pcie);
2029 ret = tegra_pcie_get_slot_regulators(pcie);
2042 if (pcie->pex_refclk_sel_gpiod)
2043 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1);
2045 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
2046 if (IS_ERR(pcie->pex_ctl_supply)) {
2047 ret = PTR_ERR(pcie->pex_ctl_supply);
2050 PTR_ERR(pcie->pex_ctl_supply));
2054 pcie->core_clk = devm_clk_get(dev, "core");
2055 if (IS_ERR(pcie->core_clk)) {
2057 PTR_ERR(pcie->core_clk));
2058 return PTR_ERR(pcie->core_clk);
2061 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2063 if (!pcie->appl_res) {
2068 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
2069 if (IS_ERR(pcie->appl_base))
2070 return PTR_ERR(pcie->appl_base);
2072 pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
2073 if (IS_ERR(pcie->core_apb_rst)) {
2075 PTR_ERR(pcie->core_apb_rst));
2076 return PTR_ERR(pcie->core_apb_rst);
2079 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
2083 for (i = 0; i < pcie->phy_count; i++) {
2099 pcie->phys = phys;
2106 pcie->dbi_res = dbi_res;
2121 pcie->atu_dma_res = atu_dma_res;
2127 pcie->core_rst = devm_reset_control_get(dev, "core");
2128 if (IS_ERR(pcie->core_rst)) {
2130 PTR_ERR(pcie->core_rst));
2131 return PTR_ERR(pcie->core_rst);
2138 pcie->bpmp = tegra_bpmp_get(dev);
2139 if (IS_ERR(pcie->bpmp))
2140 return PTR_ERR(pcie->bpmp);
2142 platform_set_drvdata(pdev, pcie);
2144 switch (pcie->mode) {
2147 IRQF_SHARED, "tegra-pcie-intr", pcie);
2154 ret = tegra_pcie_config_rp(pcie);
2166 "tegra-pcie-ep-intr", pcie);
2173 ret = tegra_pcie_config_ep(pcie, pdev);
2179 dev_err(dev, "Invalid PCIe device type %d\n", pcie->mode);
2183 tegra_bpmp_put(pcie->bpmp);
2189 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
2191 if (!pcie->link_state)
2194 debugfs_remove_recursive(pcie->debugfs);
2195 tegra_pcie_deinit_controller(pcie);
2196 pm_runtime_put_sync(pcie->dev);
2197 pm_runtime_disable(pcie->dev);
2198 tegra_bpmp_put(pcie->bpmp);
2199 if (pcie->pex_refclk_sel_gpiod)
2200 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0);
2207 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2210 if (!pcie->link_state)
2214 val = appl_readl(pcie, APPL_CTRL);
2218 appl_writel(pcie, val, APPL_CTRL);
2225 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2227 if (!pcie->link_state)
2231 pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
2233 tegra_pcie_downstream_dev_to_D0(pcie);
2234 tegra_pcie_dw_pme_turnoff(pcie);
2236 return __deinit_controller(pcie);
2241 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2244 if (!pcie->link_state)
2247 ret = tegra_pcie_config_controller(pcie, true);
2251 ret = tegra_pcie_dw_host_init(&pcie->pci.pp);
2258 dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,
2259 pcie->msi_ctrl_int);
2264 return __deinit_controller(pcie);
2269 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2272 if (!pcie->link_state)
2276 val = appl_readl(pcie, APPL_CTRL);
2282 appl_writel(pcie, val, APPL_CTRL);
2289 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
2291 if (!pcie->link_state)
2294 debugfs_remove_recursive(pcie->debugfs);
2295 tegra_pcie_downstream_dev_to_D0(pcie);
2297 disable_irq(pcie->pci.pp.irq);
2299 disable_irq(pcie->pci.pp.msi_irq);
2301 tegra_pcie_dw_pme_turnoff(pcie);
2302 __deinit_controller(pcie);
2315 .compatible = "nvidia,tegra194-pcie",
2319 .compatible = "nvidia,tegra194-pcie-ep",
2337 .name = "tegra194-pcie",