Lines Matching refs:res
188 union qcom_pcie_resources res;
236 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
241 res->supplies[0].supply = "vdda";
242 res->supplies[1].supply = "vdda_phy";
243 res->supplies[2].supply = "vdda_refclk";
244 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
245 res->supplies);
249 res->clks[0].id = "iface";
250 res->clks[1].id = "core";
251 res->clks[2].id = "phy";
252 res->clks[3].id = "aux";
253 res->clks[4].id = "ref";
256 ret = devm_clk_bulk_get(dev, 3, res->clks);
261 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
265 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
266 if (IS_ERR(res->pci_reset))
267 return PTR_ERR(res->pci_reset);
269 res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
270 if (IS_ERR(res->axi_reset))
271 return PTR_ERR(res->axi_reset);
273 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
274 if (IS_ERR(res->ahb_reset))
275 return PTR_ERR(res->ahb_reset);
277 res->por_reset = devm_reset_control_get_exclusive(dev, "por");
278 if (IS_ERR(res->por_reset))
279 return PTR_ERR(res->por_reset);
281 res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
282 if (IS_ERR(res->ext_reset))
283 return PTR_ERR(res->ext_reset);
285 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
286 return PTR_ERR_OR_ZERO(res->phy_reset);
291 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
293 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
294 reset_control_assert(res->pci_reset);
295 reset_control_assert(res->axi_reset);
296 reset_control_assert(res->ahb_reset);
297 reset_control_assert(res->por_reset);
298 reset_control_assert(res->ext_reset);
299 reset_control_assert(res->phy_reset);
303 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
308 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
316 reset_control_assert(res->pci_reset);
317 reset_control_assert(res->axi_reset);
318 reset_control_assert(res->ahb_reset);
319 reset_control_assert(res->por_reset);
320 reset_control_assert(res->ext_reset);
321 reset_control_assert(res->phy_reset);
323 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
329 ret = reset_control_deassert(res->ahb_reset);
335 ret = reset_control_deassert(res->ext_reset);
341 ret = reset_control_deassert(res->phy_reset);
347 ret = reset_control_deassert(res->pci_reset);
353 ret = reset_control_deassert(res->por_reset);
359 ret = reset_control_deassert(res->axi_reset);
370 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
414 reset_control_assert(res->axi_reset);
416 reset_control_assert(res->por_reset);
418 reset_control_assert(res->pci_reset);
420 reset_control_assert(res->phy_reset);
422 reset_control_assert(res->ext_reset);
424 reset_control_assert(res->ahb_reset);
426 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
433 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
437 res->vdda = devm_regulator_get(dev, "vdda");
438 if (IS_ERR(res->vdda))
439 return PTR_ERR(res->vdda);
441 res->iface = devm_clk_get(dev, "iface");
442 if (IS_ERR(res->iface))
443 return PTR_ERR(res->iface);
445 res->aux = devm_clk_get(dev, "aux");
446 if (IS_ERR(res->aux))
447 return PTR_ERR(res->aux);
449 res->master_bus = devm_clk_get(dev, "master_bus");
450 if (IS_ERR(res->master_bus))
451 return PTR_ERR(res->master_bus);
453 res->slave_bus = devm_clk_get(dev, "slave_bus");
454 if (IS_ERR(res->slave_bus))
455 return PTR_ERR(res->slave_bus);
457 res->core = devm_reset_control_get_exclusive(dev, "core");
458 return PTR_ERR_OR_ZERO(res->core);
463 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
465 reset_control_assert(res->core);
466 clk_disable_unprepare(res->slave_bus);
467 clk_disable_unprepare(res->master_bus);
468 clk_disable_unprepare(res->iface);
469 clk_disable_unprepare(res->aux);
470 regulator_disable(res->vdda);
475 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
480 ret = reset_control_deassert(res->core);
486 ret = clk_prepare_enable(res->aux);
492 ret = clk_prepare_enable(res->iface);
498 ret = clk_prepare_enable(res->master_bus);
504 ret = clk_prepare_enable(res->slave_bus);
510 ret = regulator_enable(res->vdda);
528 clk_disable_unprepare(res->slave_bus);
530 clk_disable_unprepare(res->master_bus);
532 clk_disable_unprepare(res->iface);
534 clk_disable_unprepare(res->aux);
536 reset_control_assert(res->core);
553 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
558 res->supplies[0].supply = "vdda";
559 res->supplies[1].supply = "vddpe-3v3";
560 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
561 res->supplies);
565 res->aux_clk = devm_clk_get(dev, "aux");
566 if (IS_ERR(res->aux_clk))
567 return PTR_ERR(res->aux_clk);
569 res->cfg_clk = devm_clk_get(dev, "cfg");
570 if (IS_ERR(res->cfg_clk))
571 return PTR_ERR(res->cfg_clk);
573 res->master_clk = devm_clk_get(dev, "bus_master");
574 if (IS_ERR(res->master_clk))
575 return PTR_ERR(res->master_clk);
577 res->slave_clk = devm_clk_get(dev, "bus_slave");
578 if (IS_ERR(res->slave_clk))
579 return PTR_ERR(res->slave_clk);
581 res->pipe_clk = devm_clk_get(dev, "pipe");
582 return PTR_ERR_OR_ZERO(res->pipe_clk);
587 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
589 clk_disable_unprepare(res->slave_clk);
590 clk_disable_unprepare(res->master_clk);
591 clk_disable_unprepare(res->cfg_clk);
592 clk_disable_unprepare(res->aux_clk);
594 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
599 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
601 clk_disable_unprepare(res->pipe_clk);
606 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
612 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
618 ret = clk_prepare_enable(res->aux_clk);
624 ret = clk_prepare_enable(res->cfg_clk);
630 ret = clk_prepare_enable(res->master_clk);
636 ret = clk_prepare_enable(res->slave_clk);
666 clk_disable_unprepare(res->master_clk);
668 clk_disable_unprepare(res->cfg_clk);
670 clk_disable_unprepare(res->aux_clk);
673 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
680 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
685 ret = clk_prepare_enable(res->pipe_clk);
696 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
702 res->clks[0].id = "aux";
703 res->clks[1].id = "master_bus";
704 res->clks[2].id = "slave_bus";
705 res->clks[3].id = "iface";
708 res->num_clks = is_ipq ? 3 : 4;
710 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
714 res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
715 if (IS_ERR(res->axi_m_reset))
716 return PTR_ERR(res->axi_m_reset);
718 res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
719 if (IS_ERR(res->axi_s_reset))
720 return PTR_ERR(res->axi_s_reset);
727 res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
728 if (IS_ERR(res->pipe_reset))
729 return PTR_ERR(res->pipe_reset);
731 res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
733 if (IS_ERR(res->axi_m_vmid_reset))
734 return PTR_ERR(res->axi_m_vmid_reset);
736 res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
738 if (IS_ERR(res->axi_s_xpu_reset))
739 return PTR_ERR(res->axi_s_xpu_reset);
741 res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
742 if (IS_ERR(res->parf_reset))
743 return PTR_ERR(res->parf_reset);
745 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
746 if (IS_ERR(res->phy_reset))
747 return PTR_ERR(res->phy_reset);
750 res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
752 if (IS_ERR(res->axi_m_sticky_reset))
753 return PTR_ERR(res->axi_m_sticky_reset);
755 res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
757 if (IS_ERR(res->pipe_sticky_reset))
758 return PTR_ERR(res->pipe_sticky_reset);
760 res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
761 if (IS_ERR(res->pwr_reset))
762 return PTR_ERR(res->pwr_reset);
764 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
765 if (IS_ERR(res->ahb_reset))
766 return PTR_ERR(res->ahb_reset);
769 res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
770 if (IS_ERR(res->phy_ahb_reset))
771 return PTR_ERR(res->phy_ahb_reset);
779 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
781 reset_control_assert(res->axi_m_reset);
782 reset_control_assert(res->axi_s_reset);
783 reset_control_assert(res->pipe_reset);
784 reset_control_assert(res->pipe_sticky_reset);
785 reset_control_assert(res->phy_reset);
786 reset_control_assert(res->phy_ahb_reset);
787 reset_control_assert(res->axi_m_sticky_reset);
788 reset_control_assert(res->pwr_reset);
789 reset_control_assert(res->ahb_reset);
790 clk_bulk_disable_unprepare(res->num_clks, res->clks);
795 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
801 ret = reset_control_assert(res->axi_m_reset);
807 ret = reset_control_assert(res->axi_s_reset);
815 ret = reset_control_assert(res->pipe_reset);
821 ret = reset_control_assert(res->pipe_sticky_reset);
827 ret = reset_control_assert(res->phy_reset);
833 ret = reset_control_assert(res->phy_ahb_reset);
841 ret = reset_control_assert(res->axi_m_sticky_reset);
847 ret = reset_control_assert(res->pwr_reset);
853 ret = reset_control_assert(res->ahb_reset);
861 ret = reset_control_deassert(res->phy_ahb_reset);
867 ret = reset_control_deassert(res->phy_reset);
873 ret = reset_control_deassert(res->pipe_reset);
879 ret = reset_control_deassert(res->pipe_sticky_reset);
887 ret = reset_control_deassert(res->axi_m_reset);
893 ret = reset_control_deassert(res->axi_m_sticky_reset);
899 ret = reset_control_deassert(res->axi_s_reset);
905 ret = reset_control_deassert(res->pwr_reset);
911 ret = reset_control_deassert(res->ahb_reset);
919 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
947 reset_control_assert(res->ahb_reset);
949 reset_control_assert(res->pwr_reset);
951 reset_control_assert(res->axi_s_reset);
953 reset_control_assert(res->axi_m_sticky_reset);
955 reset_control_assert(res->axi_m_reset);
957 reset_control_assert(res->pipe_sticky_reset);
959 reset_control_assert(res->pipe_reset);
961 reset_control_assert(res->phy_reset);
963 reset_control_assert(res->phy_ahb_reset);
969 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
977 res->iface = devm_clk_get(dev, "iface");
978 if (IS_ERR(res->iface))
979 return PTR_ERR(res->iface);
981 res->axi_m_clk = devm_clk_get(dev, "axi_m");
982 if (IS_ERR(res->axi_m_clk))
983 return PTR_ERR(res->axi_m_clk);
985 res->axi_s_clk = devm_clk_get(dev, "axi_s");
986 if (IS_ERR(res->axi_s_clk))
987 return PTR_ERR(res->axi_s_clk);
989 res->ahb_clk = devm_clk_get(dev, "ahb");
990 if (IS_ERR(res->ahb_clk))
991 return PTR_ERR(res->ahb_clk);
993 res->aux_clk = devm_clk_get(dev, "aux");
994 if (IS_ERR(res->aux_clk))
995 return PTR_ERR(res->aux_clk);
998 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
999 if (IS_ERR(res->rst[i]))
1000 return PTR_ERR(res->rst[i]);
1008 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1010 clk_disable_unprepare(res->iface);
1011 clk_disable_unprepare(res->axi_m_clk);
1012 clk_disable_unprepare(res->axi_s_clk);
1013 clk_disable_unprepare(res->ahb_clk);
1014 clk_disable_unprepare(res->aux_clk);
1019 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1026 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1027 ret = reset_control_assert(res->rst[i]);
1036 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1037 ret = reset_control_deassert(res->rst[i]);
1051 ret = clk_prepare_enable(res->iface);
1057 ret = clk_prepare_enable(res->axi_m_clk);
1063 ret = clk_prepare_enable(res->axi_s_clk);
1069 ret = clk_prepare_enable(res->ahb_clk);
1075 ret = clk_prepare_enable(res->aux_clk);
1110 clk_disable_unprepare(res->ahb_clk);
1112 clk_disable_unprepare(res->axi_s_clk);
1114 clk_disable_unprepare(res->axi_m_clk);
1116 clk_disable_unprepare(res->iface);
1122 for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1123 reset_control_assert(res->rst[i]);
1130 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1135 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
1136 if (IS_ERR(res->pci_reset))
1137 return PTR_ERR(res->pci_reset);
1139 res->supplies[0].supply = "vdda";
1140 res->supplies[1].supply = "vddpe-3v3";
1141 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
1142 res->supplies);
1146 res->clks[0].id = "aux";
1147 res->clks[1].id = "cfg";
1148 res->clks[2].id = "bus_master";
1149 res->clks[3].id = "bus_slave";
1150 res->clks[4].id = "slave_q2a";
1151 res->clks[5].id = "tbu";
1153 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
1157 res->pipe_clk = devm_clk_get(dev, "pipe");
1158 return PTR_ERR_OR_ZERO(res->pipe_clk);
1163 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1169 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
1175 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
1179 ret = reset_control_assert(res->pci_reset);
1187 ret = reset_control_deassert(res->pci_reset);
1219 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
1221 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1228 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1230 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
1231 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1236 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1238 return clk_prepare_enable(res->pipe_clk);
1243 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1245 clk_disable_unprepare(res->pipe_clk);
1363 struct resource *res;
1402 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1403 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);