Lines Matching refs:pcie
31 #include "pcie-designware.h"
176 int (*get_resources)(struct qcom_pcie *pcie);
177 int (*init)(struct qcom_pcie *pcie);
178 int (*post_init)(struct qcom_pcie *pcie);
179 void (*deinit)(struct qcom_pcie *pcie);
180 void (*post_deinit)(struct qcom_pcie *pcie);
181 void (*ltssm_enable)(struct qcom_pcie *pcie);
196 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
198 gpiod_set_value_cansleep(pcie->reset, 1);
202 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
206 gpiod_set_value_cansleep(pcie->reset, 0);
210 static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
212 struct dw_pcie *pci = pcie->pci;
218 if (pcie->ops->ltssm_enable)
219 pcie->ops->ltssm_enable(pcie);
224 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
229 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
231 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
234 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
236 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
237 struct dw_pcie *pci = pcie->pci;
289 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
291 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
301 writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
306 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
308 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
309 struct dw_pcie *pci = pcie->pci;
366 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
368 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
374 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
375 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
379 pcie->parf + PCIE20_PARF_PCS_DEEMPH);
382 pcie->parf + PCIE20_PARF_PCS_SWING);
383 writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
386 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
388 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
391 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
395 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
397 if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
400 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
431 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
433 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
434 struct dw_pcie *pci = pcie->pci;
461 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
463 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
473 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
475 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
476 struct dw_pcie *pci = pcie->pci;
517 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
520 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
523 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
541 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
546 val = readl(pcie->parf + PCIE20_PARF_LTSSM);
548 writel(val, pcie->parf + PCIE20_PARF_LTSSM);
551 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
553 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
554 struct dw_pcie *pci = pcie->pci;
585 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
587 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
597 static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
599 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
604 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
606 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
607 struct dw_pcie *pci = pcie->pci;
643 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
645 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
648 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
651 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
653 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
655 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
657 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
659 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
661 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
678 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
680 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
681 struct dw_pcie *pci = pcie->pci;
694 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
696 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
697 struct dw_pcie *pci = pcie->pci;
699 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
707 /* qcom,pcie-ipq4019 is defined without "iface" */
777 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
779 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
793 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
795 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
796 struct dw_pcie *pci = pcie->pci;
924 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
926 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
929 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
932 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
934 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
936 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
938 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
940 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
942 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
967 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
969 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
970 struct dw_pcie *pci = pcie->pci;
1006 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
1008 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1017 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
1019 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1020 struct dw_pcie *pci = pcie->pci;
1082 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1084 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1086 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1088 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1093 pcie->parf + PCIE20_PARF_SYS_CTRL);
1094 writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1128 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
1130 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1131 struct dw_pcie *pci = pcie->pci;
1161 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
1163 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1164 struct dw_pcie *pci = pcie->pci;
1194 writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
1197 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1199 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1202 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1205 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
1207 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
1209 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1211 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1213 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
1215 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
1226 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
1228 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1234 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
1236 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1241 static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)
1243 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1259 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1262 qcom_ep_reset_assert(pcie);
1264 ret = pcie->ops->init(pcie);
1268 ret = phy_power_on(pcie->phy);
1272 if (pcie->ops->post_init) {
1273 ret = pcie->ops->post_init(pcie);
1281 qcom_ep_reset_deassert(pcie);
1283 ret = qcom_pcie_establish_link(pcie);
1289 qcom_ep_reset_assert(pcie);
1290 if (pcie->ops->post_deinit)
1291 pcie->ops->post_deinit(pcie);
1293 phy_power_off(pcie->phy);
1295 pcie->ops->deinit(pcie);
1366 struct qcom_pcie *pcie;
1369 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1370 if (!pcie)
1386 pcie->pci = pci;
1388 pcie->ops = of_device_get_match_data(dev);
1390 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1391 if (IS_ERR(pcie->reset)) {
1392 ret = PTR_ERR(pcie->reset);
1396 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1397 if (IS_ERR(pcie->parf)) {
1398 ret = PTR_ERR(pcie->parf);
1409 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1410 if (IS_ERR(pcie->elbi)) {
1411 ret = PTR_ERR(pcie->elbi);
1415 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1416 if (IS_ERR(pcie->phy)) {
1417 ret = PTR_ERR(pcie->phy);
1421 ret = pcie->ops->get_resources(pcie);
1435 ret = phy_init(pcie->phy);
1439 platform_set_drvdata(pdev, pcie);
1450 phy_exit(pcie->phy);
1459 { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
1460 { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
1461 { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
1462 { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
1463 { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
1464 { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
1465 { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
1466 { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
1467 { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
1486 .name = "qcom-pcie",