Lines Matching refs:pci
16 #include "../../pci.h"
24 static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
33 reg = dw_pcie_readw_dbi(pci, cap_ptr);
43 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
46 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
51 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
54 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
58 static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
71 header = dw_pcie_readl_dbi(pci, pos);
87 header = dw_pcie_readl_dbi(pci, pos);
93 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
95 return dw_pcie_find_next_ext_capability(pci, 0, cap);
139 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
144 if (pci->ops->read_dbi)
145 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
147 ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
149 dev_err(pci->dev, "Read DBI address failed\n");
155 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
159 if (pci->ops->write_dbi) {
160 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
164 ret = dw_pcie_write(pci->dbi_base + reg, size, val);
166 dev_err(pci->dev, "Write DBI address failed\n");
170 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
174 if (pci->ops->write_dbi2) {
175 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
179 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
181 dev_err(pci->dev, "write DBI address failed\n");
184 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg)
189 if (pci->ops->read_dbi)
190 return pci->ops->read_dbi(pci, pci->atu_base, reg, 4);
192 ret = dw_pcie_read(pci->atu_base + reg, 4, &val);
194 dev_err(pci->dev, "Read ATU address failed\n");
199 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)
203 if (pci->ops->write_dbi) {
204 pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val);
208 ret = dw_pcie_write(pci->atu_base + reg, 4, val);
210 dev_err(pci->dev, "Write ATU address failed\n");
213 static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
217 return dw_pcie_readl_atu(pci, offset + reg);
220 static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
225 dw_pcie_writel_atu(pci, offset + reg, val);
228 static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
236 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
238 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
240 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT,
242 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
244 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
246 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
248 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
250 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
258 val = dw_pcie_readl_ob_unroll(pci, index,
265 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
268 static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
274 if (pci->ops->cpu_addr_fixup)
275 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
277 if (pci->iatu_unroll_enabled) {
278 dw_pcie_prog_outbound_atu_unroll(pci, func_no, index, type,
283 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
285 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
287 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
289 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
291 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
293 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
295 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
297 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
304 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
310 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
313 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
316 __dw_pcie_prog_outbound_atu(pci, 0, index, type,
320 void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
324 __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
328 static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
332 return dw_pcie_readl_atu(pci, offset + reg);
335 static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
340 dw_pcie_writel_atu(pci, offset + reg, val);
343 static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
350 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
352 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
366 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type |
368 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
378 val = dw_pcie_readl_ib_unroll(pci, index,
385 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
390 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
397 if (pci->iatu_unroll_enabled)
398 return dw_pcie_prog_inbound_atu_unroll(pci, func_no, index, bar,
401 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
403 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
404 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
417 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
419 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE |
428 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
434 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
439 void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
455 if (pci->iatu_unroll_enabled) {
457 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
460 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
464 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
465 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE);
469 int dw_pcie_wait_for_link(struct dw_pcie *pci)
475 if (dw_pcie_link_up(pci)) {
476 dev_info(pci->dev, "Link up\n");
482 dev_info(pci->dev, "Phy link never came up\n");
488 int dw_pcie_link_up(struct dw_pcie *pci)
492 if (pci->ops->link_up)
493 return pci->ops->link_up(pci);
495 val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
500 void dw_pcie_upconfig_setup(struct dw_pcie *pci)
504 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
506 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
510 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
513 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
515 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
516 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
539 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
542 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
546 static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
550 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
557 void dw_pcie_setup(struct dw_pcie *pci)
560 struct device *dev = pci->dev;
564 if (pci->version >= 0x480A || (!pci->version &&
565 dw_pcie_iatu_unroll_enabled(pci))) {
566 pci->iatu_unroll_enabled = true;
567 if (!pci->atu_base)
568 pci->atu_base =
570 if (IS_ERR(pci->atu_base))
571 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
573 dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
576 if (pci->link_gen > 0)
577 dw_pcie_link_set_max_speed(pci, pci->link_gen);
580 if (pci->n_fts[0]) {
581 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
583 val |= PORT_AFR_N_FTS(pci->n_fts[0]);
584 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]);
585 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
589 if (pci->n_fts[1]) {
590 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
592 val |= pci->n_fts[1];
593 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
596 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
599 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
602 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
605 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
608 of_property_read_u32(np, "num-lanes", &pci->num_lanes);
609 if (!pci->num_lanes) {
610 dev_dbg(pci->dev, "Using h/w default number of lanes\n");
617 switch (pci->num_lanes) {
631 dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
634 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
637 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
639 switch (pci->num_lanes) {
653 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);