Lines Matching defs:pcie
26 struct al_pcie_acpi *pcie = cfg->priv;
27 void __iomem *dbi_base = pcie->dbi_base;
93 #include "pcie-designware.h"
145 static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset)
147 return readl_relaxed(pcie->controller_base + offset);
150 static inline void al_pcie_controller_writel(struct al_pcie *pcie, u32 offset,
153 writel_relaxed(val, pcie->controller_base + offset);
156 static int al_pcie_rev_id_get(struct al_pcie *pcie, unsigned int *rev_id)
161 dev_rev_id_val = al_pcie_controller_readl(pcie, AXI_BASE_OFFSET +
177 dev_err(pcie->dev, "Unsupported dev_id_val (0x%x)\n",
182 dev_dbg(pcie->dev, "dev_id_val: 0x%x\n", dev_id_val);
187 static int al_pcie_reg_offsets_set(struct al_pcie *pcie)
189 switch (pcie->controller_rev_id) {
191 pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET;
195 pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET;
198 dev_err(pcie->dev, "Unsupported controller rev_id: 0x%x\n",
199 pcie->controller_rev_id);
206 static inline void al_pcie_target_bus_set(struct al_pcie *pcie,
215 al_pcie_controller_writel(pcie, AXI_BASE_OFFSET +
216 pcie->reg_offsets.ob_ctrl + CFG_TARGET_BUS,
224 struct al_pcie *pcie = to_al_pcie(to_dw_pcie_from_pp(pp));
226 struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg;
236 dev_dbg(pcie->pci->dev, "Changing target bus busnum val from 0x%x to 0x%x\n",
239 al_pcie_target_bus_set(pcie,
253 static void al_pcie_config_prepare(struct al_pcie *pcie)
256 struct pcie_port *pp = &pcie->pci->pp;
265 target_bus_cfg = &pcie->target_bus_cfg;
267 ecam_bus_mask = (pcie->ecam_size >> 20) - 1;
269 dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n");
279 al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val,
286 cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl +
289 cfg_control = al_pcie_controller_readl(pcie, cfg_control_offset);
297 al_pcie_controller_writel(pcie, cfg_control_offset, reg);
303 struct al_pcie *pcie = to_al_pcie(pci);
308 rc = al_pcie_rev_id_get(pcie, &pcie->controller_rev_id);
312 rc = al_pcie_reg_offsets_set(pcie);
316 al_pcie_config_prepare(pcie);
398 { .compatible = "amazon,al-alpine-v2-pcie",
400 { .compatible = "amazon,al-alpine-v3-pcie",
407 .name = "al-pcie",