Lines Matching defs:pcie
35 #include "pcie-designware.h"
70 struct clk *pcie;
85 /* power domain for pcie */
87 /* power domain for pcie phy */
334 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
345 dev_err(dev, "Failed to add device_link to pcie pd.\n");
516 ret = clk_prepare_enable(imx6_pcie->pcie);
518 dev_err(dev, "unable to enable pcie clock\n");
524 dev_err(dev, "unable to enable pcie ref clock\n");
554 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
585 clk_disable_unprepare(imx6_pcie->pcie);
643 /* configure constant input signal to the pcie ctrl and phy */
879 /* No special ops needed, but pcie-designware still expects this struct */
939 clk_disable_unprepare(imx6_pcie->pcie);
990 dev_info(dev, "pcie link is down after resume.\n");
1027 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
1077 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
1078 if (IS_ERR(imx6_pcie->pcie))
1079 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie),
1080 "pcie clock source missing or invalid\n");
1221 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1222 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1223 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1224 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1225 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
1231 .name = "imx6q-pcie",