Lines Matching refs:addr
373 static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size)
375 void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);
376 unsigned int offset = (unsigned long)addr & 0x3;
379 if (!IS_ALIGNED((uintptr_t)addr, size)) {
380 pr_warn("Address %p and size %d are not aligned\n", addr, size);
390 static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value)
392 void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);
393 unsigned int offset = (unsigned long)addr & 0x3;
397 if (!IS_ALIGNED((uintptr_t)addr, size)) {
398 pr_warn("Address %p and size %d are not aligned\n", addr, size);
403 writel(value, addr);
417 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
419 cdns_pcie_write_sz(addr, 0x1, value);
425 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
427 cdns_pcie_write_sz(addr, 0x2, value);
432 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
434 return cdns_pcie_read_sz(addr, 0x2);
441 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;
443 cdns_pcie_write_sz(addr, 0x1, value);
449 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;
451 cdns_pcie_write_sz(addr, 0x2, value);
462 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;
464 return cdns_pcie_read_sz(addr, 0x2);