Lines Matching refs:port
2 /* Low-level parallel-port routines for 8255-based PC-style hardware.
43 * but rather will start at port->base_hi.
231 dev->port->irq != PARPORT_IRQ_NONE)
259 static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
272 status = inb(STATUS(port));
278 insl(EPPDATA(port), buf, 4);
280 insb(EPPDATA(port), buf, 16);
286 *((char *)buf) = inb(EPPDATA(port));
291 status = inb(STATUS(port));
295 port->name);
296 clear_epp_timeout(port);
303 insl(EPPDATA(port), buf, (length >> 2));
305 insb(EPPDATA(port), buf, length);
306 if (inb(STATUS(port)) & 0x01) {
307 clear_epp_timeout(port);
313 *((char *)buf) = inb(EPPDATA(port));
315 if (inb(STATUS(port)) & 0x01) {
317 clear_epp_timeout(port);
325 static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
332 outsl(EPPDATA(port), buf, (length >> 2));
334 outsb(EPPDATA(port), buf, length);
335 if (inb(STATUS(port)) & 0x01) {
336 clear_epp_timeout(port);
342 outb(*((char *)buf), EPPDATA(port));
344 if (inb(STATUS(port)) & 0x01) {
345 clear_epp_timeout(port);
353 static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
359 insb(EPPADDR(port), buf, length);
360 if (inb(STATUS(port)) & 0x01) {
361 clear_epp_timeout(port);
367 *((char *)buf) = inb(EPPADDR(port));
369 if (inb(STATUS(port)) & 0x01) {
370 clear_epp_timeout(port);
378 static size_t parport_pc_epp_write_addr(struct parport *port,
385 outsb(EPPADDR(port), buf, length);
386 if (inb(STATUS(port)) & 0x01) {
387 clear_epp_timeout(port);
393 outb(*((char *)buf), EPPADDR(port));
395 if (inb(STATUS(port)) & 0x01) {
396 clear_epp_timeout(port);
404 static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
409 frob_set_mode(port, ECR_EPP);
410 parport_pc_data_reverse(port);
411 parport_pc_write_control(port, 0x4);
412 got = parport_pc_epp_read_data(port, buf, length, flags);
413 frob_set_mode(port, ECR_PS2);
418 static size_t parport_pc_ecpepp_write_data(struct parport *port,
424 frob_set_mode(port, ECR_EPP);
425 parport_pc_write_control(port, 0x4);
426 parport_pc_data_forward(port);
427 written = parport_pc_epp_write_data(port, buf, length, flags);
428 frob_set_mode(port, ECR_PS2);
433 static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
438 frob_set_mode(port, ECR_EPP);
439 parport_pc_data_reverse(port);
440 parport_pc_write_control(port, 0x4);
441 got = parport_pc_epp_read_addr(port, buf, length, flags);
442 frob_set_mode(port, ECR_PS2);
447 static size_t parport_pc_ecpepp_write_addr(struct parport *port,
453 frob_set_mode(port, ECR_EPP);
454 parport_pc_write_control(port, 0x4);
455 parport_pc_data_forward(port);
456 written = parport_pc_epp_write_addr(port, buf, length, flags);
457 frob_set_mode(port, ECR_PS2);
464 static size_t parport_pc_fifo_write_block_pio(struct parport *port,
470 unsigned long expire = jiffies + port->physport->cad->timeout;
471 const unsigned long fifo = FIFO(port);
473 const struct parport_pc_private *priv = port->physport->private_data;
476 port = port->physport;
479 parport_pc_disable_irq(port);
481 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
484 parport_pc_data_forward(port); /* Must be in PS2 mode */
488 unsigned char ecrval = inb(ECONTROL(port));
492 /* Can't yield the port. */
495 /* Anyone else waiting for the port? */
496 if (port->waithead) {
497 printk(KERN_DEBUG "Somebody wants the port\n");
505 ECR_WRITE(port, ecrval & ~(1<<2));
507 ret = parport_wait_event(port, HZ);
516 ecrval = inb(ECONTROL(port));
529 expire = jiffies + port->cad->timeout;
548 ecrval = inb(ECONTROL(port));
557 dump_parport_state("leave fifo_write_block_pio", port);
562 static size_t parport_pc_fifo_write_block_dma(struct parport *port,
568 const struct parport_pc_private *priv = port->physport->private_data;
569 struct device *dev = port->physport->dev;
575 dump_parport_state("enter fifo_write_block_dma", port);
591 port = port->physport;
594 parport_pc_disable_irq(port);
596 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
599 parport_pc_data_forward(port); /* Must be in PS2 mode */
602 unsigned long expire = jiffies + port->physport->cad->timeout;
613 disable_dma(port->dma);
614 clear_dma_ff(port->dma);
615 set_dma_mode(port->dma, DMA_MODE_WRITE);
616 set_dma_addr(port->dma, dma_addr);
617 set_dma_count(port->dma, count);
620 frob_econtrol(port, 1<<3, 1<<3);
623 frob_econtrol(port, 1<<2, 0);
625 enable_dma(port->dma);
636 ret = parport_wait_event(port, HZ);
646 if (!(inb(ECONTROL(port)) & (1<<2))) {
653 disable_dma(port->dma);
654 clear_dma_ff(port->dma);
655 count = get_dma_residue(port->dma);
658 cond_resched(); /* Can't yield the port. */
660 /* Anyone else waiting for the port? */
661 if (port->waithead) {
662 printk(KERN_DEBUG "Somebody wants the port\n");
675 disable_dma(port->dma);
676 clear_dma_ff(port->dma);
677 left += get_dma_residue(port->dma);
681 frob_econtrol(port, 1<<3, 0);
686 dump_parport_state("leave fifo_write_block_dma", port);
691 static inline size_t parport_pc_fifo_write_block(struct parport *port,
695 if (port->dma != PARPORT_DMA_NONE)
696 return parport_pc_fifo_write_block_dma(port, buf, length);
698 return parport_pc_fifo_write_block_pio(port, buf, length);
702 static size_t parport_pc_compat_write_block_pio(struct parport *port,
709 const struct parport_pc_private *priv = port->physport->private_data;
713 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
714 return parport_ieee1284_write_compat(port, buf,
717 /* Set up parallel port FIFO mode.*/
718 parport_pc_data_forward(port); /* Must be in PS2 mode */
719 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
720 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
723 port->name);
725 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
728 written = parport_pc_fifo_write_block(port, buf, length);
738 r = change_mode(port, ECR_PS2);
744 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
747 frob_set_mode(port, ECR_TST);
751 if (inb(ECONTROL(port)) & 0x2) {
755 outb(0, FIFO(port));
759 frob_set_mode(port, ECR_PS2);
762 r = parport_wait_peripheral(port,
767 port->name, r);
769 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
776 static size_t parport_pc_ecp_write_block_pio(struct parport *port,
783 const struct parport_pc_private *priv = port->physport->private_data;
787 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
788 return parport_ieee1284_ecp_write_data(port, buf,
792 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
794 parport_frob_control(port,
801 r = parport_wait_peripheral(port,
806 port->name, r);
810 /* Set up ECP parallel port mode.*/
811 parport_pc_data_forward(port); /* Must be in PS2 mode */
812 parport_pc_frob_control(port,
816 r = change_mode(port, ECR_ECP); /* ECP FIFO */
819 port->name);
820 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
823 written = parport_pc_fifo_write_block(port, buf, length);
833 r = change_mode(port, ECR_PS2);
839 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
842 frob_set_mode(port, ECR_TST);
846 if (inb(ECONTROL(port)) & 0x2) {
850 outb(0, FIFO(port));
854 frob_set_mode(port, ECR_PS2);
857 parport_pc_data_reverse(port); /* Must be in PS2 mode */
859 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
860 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
863 port->name, r);
865 parport_frob_control(port,
868 r = parport_wait_peripheral(port,
873 port->name, r);
876 r = parport_wait_peripheral(port,
881 port->name, r);
883 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1330 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1389 * Checks for port existence, all ports support SPP MODE
1391 * 0 : No parallel port at this address
1392 * PARPORT_MODE_PCSPP : SPP port detected
1409 /* Do a simple read-write test to make sure the port exists. */
1430 * port here. */
1452 pr_info("parport 0x%lx: You gave this address, but there is probably no parallel port there!\n",
1516 * 0xff but any peripheral attached to the port may drag some or all of the
1664 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
2060 priv->port = p;
2080 /* No port. */
2204 /* Done probing. Now put the port into a sensible start-up state. */
2207 * Put the ECP detected port in PS2 mode.
2215 /* Now that we've told the sharing engine about the port, and
2355 pr_debug("ITE887x: The PARALLEL I/O port is 0x%x\n", ite8872_lpt);
2369 pr_info("parport_pc: ITE 8872 parallel port: io=0x%X",
2457 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2478 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2483 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n");
2495 pr_info("parport_pc: VIA parallel port disabled in BIOS\n");
2548 pr_info("parport_pc: VIA parallel port: io=0x%X", port1);
2557 pr_warn("parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2769 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2772 /* WCH CH382L PCI-E single parallel port card */
2843 printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
2847 printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
3157 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3324 struct parport *port;
3328 port = priv->port;
3329 dev = port->dev;
3330 parport_pc_unregister_port(port);
3337 MODULE_DESCRIPTION("PC-style parallel port driver");