Lines Matching defs:base_addr
207 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
210 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
216 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
222 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
228 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
237 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
242 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
247 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
252 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
307 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
310 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
315 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
347 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
349 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
358 LBA_CFG_RESTORE(d, d->hba.base_addr);
368 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
411 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
420 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
421 LBA_CFG_RESTORE(d, d->hba.base_addr);
456 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
458 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
460 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
464 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
485 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
515 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
538 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
934 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
992 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
1083 lba_len = ~READ_REG32(lba_dev->hba.base_addr
1186 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH);
1268 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE);
1276 rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK);
1314 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE);
1322 rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK);
1332 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L;
1333 r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1362 d->hba.base_addr,
1363 READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
1364 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
1365 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
1366 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
1368 READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
1369 READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
1370 READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
1371 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
1373 READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
1377 printk(" %Lx", READ_REG64(d->hba.base_addr + i));
1391 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1396 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1400 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
1418 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1420 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1422 WRITE_REG32(stat & ~HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1433 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1444 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
1558 lba_dev->hba.base_addr = addr;
1700 void __iomem * base_addr = ioremap(lba->hpa.start, 4096);
1709 WRITE_REG32( imask, base_addr + LBA_IMASK);
1710 WRITE_REG32( ibase, base_addr + LBA_IBASE);
1711 iounmap(base_addr);