Lines Matching defs:READ_REG32
137 #define READ_REG32(addr) readl(addr)
207 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
210 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
216 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
242 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
252 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
290 error_status = READ_REG32(base + LBA_ERROR_STATUS); \
315 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
355 case 4: data = READ_REG32(data_reg); break;
397 case 4: *data = READ_REG32(data_reg); break;
464 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
499 *data = READ_REG32(data_reg); break;
1083 lba_len = ~READ_REG32(lba_dev->hba.base_addr
1186 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH);
1268 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE);
1276 rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK);
1314 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE);
1322 rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK);
1332 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L;
1333 r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1391 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1396 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1418 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1433 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1487 func_class = READ_REG32(addr + LBA_FCLASS);