Lines Matching defs:efuse
51 static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg,
56 data = readl(efuse->base + reg);
60 writel(data, efuse->base + reg);
63 static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse)
67 err = clk_prepare_enable(efuse->core_clk);
71 /* power up the efuse */
72 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
75 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4,
81 static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse)
83 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
87 clk_disable_unprepare(efuse->core_clk);
90 static int meson_mx_efuse_read_addr(struct meson_mx_efuse *efuse,
98 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
102 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
105 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
109 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
112 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
119 readl(efuse->base + MESON_MX_EFUSE_CNTL1);
121 err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1,
126 dev_err(efuse->config.dev,
127 "Timeout while reading efuse address %u\n", addr);
131 *value = readl(efuse->base + MESON_MX_EFUSE_CNTL2);
139 struct meson_mx_efuse *efuse = context;
143 err = meson_mx_efuse_hw_enable(efuse);
147 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
151 for (i = 0; i < bytes; i += efuse->config.word_size) {
152 addr = (offset + i) / efuse->config.word_size;
154 err = meson_mx_efuse_read_addr(efuse, addr, &tmp);
159 min_t(size_t, bytes - i, efuse->config.word_size));
162 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
165 meson_mx_efuse_hw_disable(efuse);
171 .name = "meson6-efuse",
176 .name = "meson8-efuse",
181 .name = "meson8b-efuse",
186 { .compatible = "amlogic,meson6-efuse", .data = &meson6_efuse_data },
187 { .compatible = "amlogic,meson8-efuse", .data = &meson8_efuse_data },
188 { .compatible = "amlogic,meson8b-efuse", .data = &meson8b_efuse_data },
196 struct meson_mx_efuse *efuse;
203 efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
204 if (!efuse)
208 efuse->base = devm_ioremap_resource(&pdev->dev, res);
209 if (IS_ERR(efuse->base))
210 return PTR_ERR(efuse->base);
212 efuse->config.name = devm_kstrdup(&pdev->dev, drvdata->name,
214 efuse->config.owner = THIS_MODULE;
215 efuse->config.dev = &pdev->dev;
216 efuse->config.priv = efuse;
217 efuse->config.stride = drvdata->word_size;
218 efuse->config.word_size = drvdata->word_size;
219 efuse->config.size = SZ_512;
220 efuse->config.read_only = true;
221 efuse->config.reg_read = meson_mx_efuse_read;
223 efuse->core_clk = devm_clk_get(&pdev->dev, "core");
224 if (IS_ERR(efuse->core_clk)) {
226 return PTR_ERR(efuse->core_clk);
229 efuse->nvmem = devm_nvmem_register(&pdev->dev, &efuse->config);
231 return PTR_ERR_OR_ZERO(efuse->nvmem);
237 .name = "meson-mx-efuse",