Lines Matching refs:start
582 .mem = { .start = 0x00A00000, .size = 0x00012000 },
583 .reg = { .start = 0x00807000, .size = 0x00005000 },
584 .mem2 = { .start = 0x00800000, .size = 0x0000B000 },
585 .mem3 = { .start = 0x00401594, .size = 0x00001020 },
588 .mem = { .start = 0x00000000, .size = 0x00014000 },
589 .reg = { .start = 0x00810000, .size = 0x0000BFFF },
590 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
591 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
594 .mem = { .start = 0x00700000, .size = 0x0000030c },
595 .reg = { .start = 0x00802000, .size = 0x00014578 },
596 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
597 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
600 .mem = { .start = 0x00800000, .size = 0x000050FC },
601 .reg = { .start = 0x00B00404, .size = 0x00001000 },
602 .mem2 = { .start = 0x00C00000, .size = 0x00000400 },
603 .mem3 = { .start = 0x00401594, .size = 0x00001020 },
606 .mem = { .start = WL18XX_PHY_INIT_MEM_ADDR,
608 .reg = { .start = 0x00000000, .size = 0x00000000 },
609 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
610 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
827 /* disable auto calibration on start*/