Lines Matching refs:wl
597 static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
601 if (wl->chip.id != CHIP_ID_128X_PG20) {
602 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
603 struct wl12xx_priv *priv = wl->priv;
617 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, priv->rx_mem_addr,
626 static int wl12xx_identify_chip(struct wl1271 *wl)
630 switch (wl->chip.id) {
633 wl->chip.id);
635 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
639 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
640 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
641 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
642 sizeof(wl->conf.mem));
645 wl->ops->prepare_read = wl127x_prepare_read;
647 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
656 wl->chip.id);
658 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
662 wl->plt_fw_name = WL127X_PLT_FW_NAME;
663 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
664 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
665 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
666 sizeof(wl->conf.mem));
669 wl->ops->prepare_read = wl127x_prepare_read;
671 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
680 wl->chip.id);
681 wl->plt_fw_name = WL128X_PLT_FW_NAME;
682 wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
683 wl->mr_fw_name = WL128X_FW_NAME_MULTI;
686 wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
691 wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER,
699 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
704 wl->fw_mem_block_size = 256;
705 wl->fwlog_end = 0x2000000;
708 wl->scan_templ_id_2_4 = CMD_TEMPL_APP_PROBE_REQ_2_4_LEGACY;
709 wl->scan_templ_id_5 = CMD_TEMPL_APP_PROBE_REQ_5_LEGACY;
710 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
711 wl->sched_scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
712 wl->max_channels_5 = WL12XX_MAX_CHANNELS_5GHZ;
713 wl->ba_rx_session_count_max = WL12XX_RX_BA_MAX_SESSIONS;
718 static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
725 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
730 ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
735 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
743 static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
752 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
757 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
763 ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
785 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
791 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
798 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
803 ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
814 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
819 ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
829 static bool wl128x_is_fref_valid(struct wl1271 *wl)
834 ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
844 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
848 ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
852 ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
856 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
863 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
868 struct wl12xx_priv *priv = wl->priv;
872 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
879 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
886 return wl128x_manually_configure_mcs_pll(wl);
891 ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
899 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
911 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
913 struct wl12xx_priv *priv = wl->priv;
920 if (!wl128x_switch_tcxo_to_fref(wl))
926 ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
938 if (!wl128x_switch_tcxo_to_fref(wl))
944 if (!wl128x_is_tcxo_valid(wl))
951 if (!wl128x_is_fref_valid(wl))
956 return wl128x_configure_mcs_pll(wl, *selected_clock);
959 static int wl127x_boot_clk(struct wl1271 *wl)
961 struct wl12xx_priv *priv = wl->priv;
966 if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
967 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
985 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
990 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
995 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
1000 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
1006 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
1012 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
1017 ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
1021 ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
1029 ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
1035 static int wl1271_boot_soft_reset(struct wl1271 *wl)
1042 ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1049 ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1068 ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1073 ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
1079 static int wl12xx_pre_boot(struct wl1271 *wl)
1081 struct wl12xx_priv *priv = wl->priv;
1086 if (wl->chip.id == CHIP_ID_128X_PG20) {
1087 ret = wl128x_boot_clk(wl, &selected_clock);
1091 ret = wl127x_boot_clk(wl);
1097 ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1103 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1111 ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1117 if (wl->chip.id == CHIP_ID_128X_PG20)
1122 ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1126 ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1131 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1135 ret = wl1271_boot_soft_reset(wl);
1143 static int wl12xx_pre_upload(struct wl1271 *wl)
1153 ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1157 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1164 ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1171 if (wl->chip.id == CHIP_ID_128X_PG20) {
1172 ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1178 ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1184 ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1190 static int wl12xx_enable_interrupts(struct wl1271 *wl)
1194 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1199 wlcore_enable_interrupts(wl);
1200 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1205 ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1212 wlcore_disable_interrupts(wl);
1218 static int wl12xx_boot(struct wl1271 *wl)
1222 ret = wl12xx_pre_boot(wl);
1226 ret = wlcore_boot_upload_nvs(wl);
1230 ret = wl12xx_pre_upload(wl);
1234 ret = wlcore_boot_upload_firmware(wl);
1238 wl->event_mask = BSS_LOSE_EVENT_ID |
1254 wl->ap_event_mask = MAX_TX_RETRY_EVENT_ID;
1256 ret = wlcore_boot_run_firmware(wl);
1260 ret = wl12xx_enable_interrupts(wl);
1266 static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1271 ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1275 ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1280 static int wl12xx_ack_event(struct wl1271 *wl)
1282 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1286 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1289 u32 align_len = wlcore_calc_packet_alignment(wl, len);
1295 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1298 if (wl->chip.id == CHIP_ID_128X_PG20) {
1307 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1310 u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1312 if (wl->chip.id == CHIP_ID_128X_PG20) {
1342 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1350 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1363 static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1365 if (wl->fw_status->tx_results_counter ==
1366 (wl->tx_results_count & 0xff))
1369 return wlcore_tx_complete(wl);
1372 static int wl12xx_hw_init(struct wl1271 *wl)
1376 if (wl->chip.id == CHIP_ID_128X_PG20) {
1379 ret = wl128x_cmd_general_parms(wl);
1385 * in wl->fem_manuf. No need to continue further
1387 if (wl->plt_mode == PLT_FEM_DETECT)
1390 ret = wl128x_cmd_radio_parms(wl);
1394 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1399 ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1403 ret = wl1271_cmd_general_parms(wl);
1409 * in wl->fem_manuf. No need to continue further
1411 if (wl->plt_mode == PLT_FEM_DETECT)
1414 ret = wl1271_cmd_radio_parms(wl);
1417 ret = wl1271_cmd_ext_radio_parms(wl);
1425 static void wl12xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status,
1456 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1462 static void wl12xx_conf_init(struct wl1271 *wl)
1464 struct wl12xx_priv *priv = wl->priv;
1467 memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1473 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1478 if (wl->chip.id == CHIP_ID_128X_PG20) {
1479 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1480 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1486 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1487 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1501 static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1507 ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1513 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1517 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1521 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1526 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1528 wl->fuse_nic_addr = mac1 & 0xffffff;
1530 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1536 static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1541 if (wl->chip.id == CHIP_ID_128X_PG20)
1542 ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1545 ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1554 static int wl12xx_get_mac(struct wl1271 *wl)
1556 if (wl12xx_mac_in_fuse(wl))
1557 return wl12xx_get_fuse_mac(wl);
1562 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1569 static int wl12xx_plt_init(struct wl1271 *wl)
1573 ret = wl->ops->boot(wl);
1577 ret = wl->ops->hw_init(wl);
1583 * in wl->fem_manuf. No need to continue further
1585 if (wl->plt_mode == PLT_FEM_DETECT)
1588 ret = wl1271_acx_init_mem_config(wl);
1592 ret = wl12xx_acx_mem_cfg(wl);
1597 ret = wl1271_cmd_data_path(wl, 1);
1602 ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1607 ret = wl1271_acx_pm_config(wl);
1614 kfree(wl->target_mem_map);
1615 wl->target_mem_map = NULL;
1618 mutex_unlock(&wl->mutex);
1626 wlcore_disable_interrupts(wl);
1627 mutex_lock(&wl->mutex);
1632 static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1640 static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1645 return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1648 static int wl12xx_set_peer_cap(struct wl1271 *wl,
1653 return wl1271_acx_set_ht_capabilities(wl, ht_cap, allow_ht_operation,
1657 static bool wl12xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1662 if (test_bit(hlid, &wl->fw_fast_lnk_map))
1663 thold = wl->conf.tx.fast_link_thold;
1665 thold = wl->conf.tx.slow_link_thold;
1670 static bool wl12xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1677 static u32 wl12xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr)
1682 static int wl12xx_setup(struct wl1271 *wl);
1797 static int wl12xx_setup(struct wl1271 *wl)
1799 struct wl12xx_priv *priv = wl->priv;
1800 struct wlcore_platdev_data *pdev_data = dev_get_platdata(&wl->pdev->dev);
1806 wl->rtable = wl12xx_rtable;
1807 wl->num_tx_desc = WL12XX_NUM_TX_DESCRIPTORS;
1808 wl->num_rx_desc = WL12XX_NUM_RX_DESCRIPTORS;
1809 wl->num_links = WL12XX_MAX_LINKS;
1810 wl->max_ap_stations = WL12XX_MAX_AP_STATIONS;
1811 wl->iface_combinations = wl12xx_iface_combinations;
1812 wl->n_iface_combinations = ARRAY_SIZE(wl12xx_iface_combinations);
1813 wl->num_mac_addr = WL12XX_NUM_MAC_ADDRESSES;
1814 wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1815 wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1816 wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1817 wl->fw_status_len = sizeof(struct wl12xx_fw_status);
1818 wl->fw_status_priv_len = 0;
1819 wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1820 wl->ofdm_only_ap = true;
1821 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ, &wl12xx_ht_cap);
1822 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ, &wl12xx_ht_cap);
1823 wl12xx_conf_init(wl);
1894 struct wl1271 *wl;
1907 wl = hw->priv;
1908 wl->ops = &wl12xx_ops;
1909 wl->ptable = wl12xx_ptable;
1910 ret = wlcore_probe(wl, pdev);
1917 wlcore_free_hw(wl);
1924 struct wl1271 *wl = platform_get_drvdata(pdev);
1927 if (!wl)
1929 priv = wl->priv;