Lines Matching refs:rtwdev
21 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
30 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
32 struct rtw_efuse *efuse = &rtwdev->efuse;
55 switch (rtw_hci_type(rtwdev)) {
67 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre)
69 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
70 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON);
71 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
72 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON);
75 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
77 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
80 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev,
96 backup[i].val = rtw_read32(rtwdev, addrs[i]);
102 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK);
109 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev,
117 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C);
123 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val);
128 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value,
157 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2)
170 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
176 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]);
177 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]);
182 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val)
246 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value)
253 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n");
259 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
266 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
270 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) &&
271 rtw8822c_dac_iq_check(rtwdev, qv[i]))
276 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev,
291 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max);
292 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max);
309 rtw_dbg(rtwdev, RTW_DBG_RFK,
312 rtw_dbg(rtwdev, RTW_DBG_RFK,
316 rtw8822c_dac_iq_sort(rtwdev, iv, qv);
319 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
322 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
330 rtw8822c_dac_iq_offset(rtwdev, iv, i_value);
331 rtw8822c_dac_iq_offset(rtwdev, qv, q_value);
334 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev,
340 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK);
341 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK);
343 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
344 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
346 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv);
347 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value);
350 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev)
352 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
353 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
354 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
355 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e);
356 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
357 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
358 rtw_write32(rtwdev, 0x1b00, 0x00000008);
359 rtw_write8(rtwdev, 0x1bcc, 0x3f);
360 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
361 rtw_write8(rtwdev, 0x1bcc, 0x3f);
362 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
363 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
366 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev,
369 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
375 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path);
391 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
393 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041);
394 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
395 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
396 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4);
397 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
398 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000);
399 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000);
401 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i);
402 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003);
403 rtw_write32(rtwdev, 0x1c24, 0x00010002);
404 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
405 rtw_dbg(rtwdev, RTW_DBG_RFK,
418 rtw_write32(rtwdev, base_addr + 0x68, temp);
420 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n",
423 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103);
424 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
425 rtw_dbg(rtwdev, RTW_DBG_RFK,
436 rtw_write32(rtwdev, 0x1c3c, 0x00000003);
437 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
438 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
441 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
444 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path)
446 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
453 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
454 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
456 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
457 rtw_write32(rtwdev, 0x1c38, 0xffffffff);
459 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
460 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
461 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
462 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81);
463 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
464 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
465 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81);
466 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
467 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
469 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d);
471 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
472 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
474 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
475 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
477 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) ||
478 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff))
479 rtw_err(rtwdev, "failed to wait for dack ready\n");
480 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
482 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
483 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
484 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
485 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
486 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
489 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev,
496 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
497 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8);
498 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0);
499 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8);
501 rtw_write32(rtwdev, 0x1b00, 0x00000008);
502 rtw_write8(rtwdev, 0x1bcc, 0x03f);
503 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
504 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
505 rtw_write32(rtwdev, 0x1c3c, 0x00088103);
507 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in);
534 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in);
535 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc);
538 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path,
553 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
554 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
555 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
556 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
557 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81);
558 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
559 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf);
560 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4);
561 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
562 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81);
563 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
564 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf);
565 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4);
566 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
568 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6);
570 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
571 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
573 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
574 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
576 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) ||
577 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc))
578 rtw_err(rtwdev, "failed to write IQ vector to hardware\n");
579 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
581 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3);
582 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
586 rtw_write32(rtwdev, base_addr + 0x68, temp);
587 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
588 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
589 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
611 rtw_dbg(rtwdev, RTW_DBG_RFK,
615 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path)
619 rtw_write32(rtwdev, base_addr + 0x68, 0x0);
620 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
621 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0);
622 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1);
625 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev,
628 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
636 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i);
637 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
642 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path)
654 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr);
659 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr);
662 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev)
664 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
667 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
669 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
671 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
673 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
676 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
678 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
680 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
682 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
686 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev)
690 temp[0] = rtw_read32(rtwdev, 0x1860);
691 temp[1] = rtw_read32(rtwdev, 0x4160);
692 temp[2] = rtw_read32(rtwdev, 0x9b4);
695 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
698 rtw_write32_clr(rtwdev, 0x1830, BIT(30));
699 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
700 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A);
703 rtw_write32_clr(rtwdev, 0x4130, BIT(30));
704 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
705 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B);
707 rtw8822c_dac_cal_backup_dck(rtwdev);
708 rtw_write32_set(rtwdev, 0x1830, BIT(30));
709 rtw_write32_set(rtwdev, 0x4130, BIT(30));
711 rtw_write32(rtwdev, 0x1860, temp[0]);
712 rtw_write32(rtwdev, 0x4160, temp[1]);
713 rtw_write32(rtwdev, 0x9b4, temp[2]);
716 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev)
718 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
721 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19));
723 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val);
725 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val);
727 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19));
729 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val);
731 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val);
733 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19));
735 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val);
737 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val);
739 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19));
741 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val);
743 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val);
746 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev)
748 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
750 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0);
751 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0);
752 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0);
753 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0);
755 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0);
756 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
757 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1);
758 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1);
760 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0);
761 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
762 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1);
763 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1);
765 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0);
766 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0);
767 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0);
768 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0);
770 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0);
771 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0);
772 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1);
773 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1);
775 rtw8822c_dac_cal_restore_dck(rtwdev);
777 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7);
778 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7);
779 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7);
780 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7);
782 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1);
783 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1);
785 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0);
786 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0);
787 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0);
788 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0);
790 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0);
791 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0);
792 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1);
793 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1);
795 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1);
796 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1);
799 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev,
805 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0);
806 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2);
808 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6)
816 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path)
818 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
830 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8))
834 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
836 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value);
837 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i);
838 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1);
841 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
843 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8))
847 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
849 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value);
850 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i);
851 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1);
853 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
855 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0);
856 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0);
857 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0);
858 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0);
863 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
865 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A))
868 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B))
874 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
876 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
886 temp[0] = rtw_read32(rtwdev, 0x1860);
887 temp[1] = rtw_read32(rtwdev, 0x4160);
888 temp[2] = rtw_read32(rtwdev, 0x9b4);
890 rtw8822c_dac_cal_restore_prepare(rtwdev);
891 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) ||
892 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) ||
893 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) ||
894 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff))
897 if (!__rtw8822c_dac_cal_restore(rtwdev)) {
898 rtw_err(rtwdev, "failed to restore dack vectors\n");
902 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1);
903 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
904 rtw_write32(rtwdev, 0x1860, temp[0]);
905 rtw_write32(rtwdev, 0x4160, temp[1]);
906 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1);
907 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1);
908 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1);
909 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1);
910 rtw_write32(rtwdev, 0x9b4, temp[2]);
915 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev)
924 if (rtw8822c_dac_cal_restore(rtwdev))
929 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf);
931 rtw8822c_dac_bb_setting(rtwdev);
934 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a);
936 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A);
937 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc);
941 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a,
947 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A);
950 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b);
952 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B);
953 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc);
957 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b,
963 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B);
965 rtw_write32(rtwdev, 0x1b00, 0x00000008);
966 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
967 rtw_write8(rtwdev, 0x1bcc, 0x0);
968 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
969 rtw_write8(rtwdev, 0x1bcc, 0x0);
971 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf);
974 rtw8822c_dac_cal_backup(rtwdev);
976 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a);
977 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b);
978 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a);
979 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b);
982 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev)
987 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15));
989 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440);
990 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D);
991 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440);
996 static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8])
1000 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \
1001 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \
1006 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1007 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1);
1023 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0);
1028 static void rtw8822c_power_trim(struct rtw_dev *rtwdev)
1040 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr);
1049 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1050 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i],
1060 rtw8822c_set_power_trim(rtwdev, bb_gain);
1062 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1065 static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev)
1070 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1071 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm);
1079 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]);
1083 static void rtw8822c_pa_bias(struct rtw_dev *rtwdev)
1089 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1090 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path],
1095 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_2G_MASK, pg_pa_bias);
1097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1098 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path],
1101 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_5G_MASK, pg_pa_bias);
1105 static void rtw8822c_rf_init(struct rtw_dev *rtwdev)
1107 rtw8822c_rf_dac_cal(rtwdev);
1108 rtw8822c_rf_x2_check(rtwdev);
1109 rtw8822c_thermal_trim(rtwdev);
1110 rtw8822c_power_trim(rtwdev);
1111 rtw8822c_pa_bias(rtwdev);
1114 static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev)
1116 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1126 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
1127 dm_info->thermal_meter_lck = rtwdev->efuse.thermal_meter_k;
1130 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev)
1132 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1133 struct rtw_hal *hal = &rtwdev->hal;
1142 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
1144 rtw_write8_set(rtwdev, REG_RF_CTRL,
1146 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
1149 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1152 rtw8822c_header_file_init(rtwdev, true);
1154 rtw_phy_load_tables(rtwdev);
1156 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
1157 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00,
1161 rtw8822c_header_file_init(rtwdev, false);
1164 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
1166 rtw_phy_init(rtwdev);
1168 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000);
1169 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000);
1170 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0);
1171 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000);
1176 rtw8822c_rf_init(rtwdev);
1177 rtw8822c_pwrtrack_init(rtwdev);
1179 rtw_bf_phy_init(rtwdev);
1271 static int rtw8822c_mac_init(struct rtw_dev *rtwdev)
1279 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL);
1281 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8);
1282 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
1284 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE);
1285 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
1286 rtw_write16(rtwdev, REG_RESP_SIFS_CCK,
1288 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM,
1291 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4);
1292 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8);
1293 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8);
1294 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0);
1295 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H);
1296 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1);
1297 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H);
1298 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4);
1299 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H);
1300 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5);
1301 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H);
1303 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
1304 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
1306 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
1307 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
1311 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
1312 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
1314 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
1315 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
1316 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
1317 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
1319 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN);
1320 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC);
1323 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM);
1324 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM);
1325 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM);
1326 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM);
1327 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
1328 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
1329 rtw_write8_set(rtwdev, REG_RD_CTRL + 1,
1334 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL);
1335 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
1336 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
1338 rtw_write8_set(rtwdev, REG_MISC_CTRL,
1340 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
1341 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
1342 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
1343 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
1344 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
1346 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
1348 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
1349 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
1350 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0);
1351 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
1352 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR);
1355 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR);
1356 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR);
1357 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE);
1358 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO);
1359 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
1360 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE);
1361 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX);
1362 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE);
1363 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
1364 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
1365 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
1366 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
1367 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
1368 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
1369 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN);
1370 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
1371 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1);
1374 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F;
1377 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16);
1383 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
1384 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF);
1386 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL);
1390 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
1393 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG);
1398 static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable)
1401 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1);
1402 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1);
1403 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1);
1405 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0);
1409 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
1426 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
1457 rtw8822c_rstb_3wire(rtwdev, false);
1459 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01);
1460 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12);
1461 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb);
1462 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00);
1464 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01);
1465 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12);
1466 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb);
1467 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00);
1469 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18);
1470 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18);
1472 rtw8822c_rstb_3wire(rtwdev, true);
1475 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev)
1479 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f);
1480 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
1481 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
1482 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi);
1483 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi);
1486 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1490 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
1491 rtw_write32_set(rtwdev, REG_TXF4, BIT(20));
1492 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
1493 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
1494 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF);
1498 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
1500 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
1502 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1504 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1508 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
1510 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
1512 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1514 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1519 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969);
1521 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a);
1523 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa);
1525 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0);
1526 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
1528 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3);
1529 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b);
1530 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7);
1531 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0);
1532 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
1534 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff);
1536 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284);
1537 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
1539 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88);
1540 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4);
1541 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2);
1542 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD,
1544 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
1546 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD,
1550 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
1552 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1);
1554 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
1555 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
1556 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
1557 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20));
1558 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22);
1559 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
1561 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1563 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1566 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1568 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1571 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1573 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1578 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494);
1580 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493);
1582 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453);
1584 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452);
1586 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412);
1588 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411);
1593 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B);
1594 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1595 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0);
1596 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7);
1597 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6);
1598 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1599 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1600 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
1603 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4),
1605 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5);
1606 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
1607 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
1609 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1);
1610 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1611 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
1614 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa);
1615 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
1616 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
1618 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6);
1619 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
1622 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
1623 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1624 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1);
1625 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4);
1626 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4);
1627 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1628 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1629 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
1632 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
1633 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1634 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2);
1635 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6);
1636 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5);
1637 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1638 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1639 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
1644 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1647 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
1648 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
1649 rtw8822c_set_channel_rf(rtwdev, channel, bw);
1650 rtw8822c_toggle_igi(rtwdev);
1653 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1656 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0);
1657 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0);
1659 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1);
1660 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1);
1664 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0);
1666 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5);
1668 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1);
1671 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1674 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0);
1675 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0);
1676 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0);
1677 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0);
1678 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0);
1680 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1);
1681 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1);
1682 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1);
1683 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1);
1684 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1);
1687 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path);
1688 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path);
1691 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1693 rtw8822c_config_cck_rx_path(rtwdev, rx_path);
1694 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path);
1697 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1701 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1703 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4);
1706 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc);
1708 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1712 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1716 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11);
1717 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
1719 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12);
1720 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
1723 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33);
1724 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404);
1726 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31);
1727 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
1732 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1735 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path);
1736 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path);
1739 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
1743 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312);
1745 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111);
1747 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312);
1749 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111);
1751 rtw8822c_config_rx_path(rtwdev, rx_path);
1752 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path);
1754 rtw8822c_toggle_igi(rtwdev);
1757 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
1760 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1789 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
1800 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
1803 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1842 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
1860 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
1869 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
1872 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
1875 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
1880 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
1885 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
1915 query_phy_status(rtwdev, phy_status, pkt_stat);
1918 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
1922 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck,
1925 struct rtw_hal *hal = &rtwdev->hal;
1931 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
1932 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000,
1936 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
1937 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00,
1942 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate,
1959 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0);
1960 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD,
1964 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev)
1966 struct rtw_hal *hal = &rtwdev->hal;
1976 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm);
1991 rtw8822c_set_tx_power_diff(rtwdev, rate - 3,
1997 static int rtw8822c_set_antenna(struct rtw_dev *rtwdev,
2001 struct rtw_hal *hal = &rtwdev->hal;
2009 rtw_info(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
2019 rtw_info(rtwdev, "unsupported rx path 0x%x\n", antenna_rx);
2026 rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
2031 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
2035 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC);
2037 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr);
2040 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
2042 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2052 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN;
2053 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT);
2055 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1);
2056 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2);
2057 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3);
2058 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4);
2059 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5);
2078 crc32_cnt = rtw_read32(rtwdev, 0x2c04);
2081 crc32_cnt = rtw_read32(rtwdev, 0x2c14);
2084 crc32_cnt = rtw_read32(rtwdev, 0x2c10);
2087 crc32_cnt = rtw_read32(rtwdev, 0x2c0c);
2091 cca32_cnt = rtw_read32(rtwdev, 0x2c08);
2098 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
2099 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2);
2100 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
2101 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2);
2104 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
2105 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
2106 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
2107 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
2110 static void rtw8822c_do_lck(struct rtw_dev *rtwdev)
2114 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_CTRL, RFREG_MASK, 0x80010);
2115 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0FA);
2117 rtw_write_rf(rtwdev, RF_PATH_A, RF_AAC_CTRL, RFREG_MASK, 0x80000);
2118 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_AAC, RFREG_MASK, 0x80001);
2120 true, rtwdev, RF_PATH_A, RF_AAC_CTRL, 0x1000);
2121 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0F8);
2122 rtw_write_rf(rtwdev, RF_PATH_B, RF_SYN_CTRL, RFREG_MASK, 0x80010);
2124 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000);
2125 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x4f000);
2127 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000);
2130 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev)
2137 rtw_fw_do_iqk(rtwdev, ¶);
2140 iqk_chk = rtw_read8(rtwdev, REG_RPT_CIP);
2145 rtw_write8(rtwdev, REG_IQKSTAT, 0x0);
2147 rtw_dbg(rtwdev, RTW_DBG_RFK, "iqk counter=%d\n", counter);
2151 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev)
2154 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2158 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);
2161 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
2164 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
2165 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);
2168 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
2170 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
2172 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
2174 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL);
2177 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, 0x40000);
2180 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
2182 struct rtw_coex *coex = &rtwdev->coex;
2184 struct rtw_efuse *efuse = &rtwdev->efuse;
2201 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1);
2214 rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1);
2215 rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0);
2216 rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1);
2217 rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1);
2225 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
2226 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1);
2228 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1);
2232 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
2234 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0);
2238 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
2240 rtw_write8_mask(rtwdev, 0x66, BIT(4), 0);
2241 rtw_write8_mask(rtwdev, 0x67, BIT(0), 0);
2242 rtw_write8_mask(rtwdev, 0x42, BIT(3), 0);
2243 rtw_write8_mask(rtwdev, 0x65, BIT(7), 0);
2244 rtw_write8_mask(rtwdev, 0x73, BIT(3), 0);
2247 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
2249 struct rtw_coex *coex = &rtwdev->coex;
2251 struct rtw_efuse *efuse = &rtwdev->efuse;
2253 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
2265 rtw_coex_write_indirect_reg(rtwdev, 0x38, BIT_LTE_COEX_EN, 0x0);
2266 rtw_coex_write_indirect_reg(rtwdev, 0xa0, MASKLWORD, 0xffff);
2267 rtw_coex_write_indirect_reg(rtwdev, 0xa4, MASKLWORD, 0xffff);
2270 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
2272 struct rtw_coex *coex = &rtwdev->coex;
2281 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
2283 struct rtw_coex *coex = &rtwdev->coex;
2293 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x22);
2294 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x36);
2295 rtw_write_rf(rtwdev, RF_PATH_B, 0xde, 0xfffff, 0x22);
2296 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x36);
2299 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x20);
2300 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x0);
2301 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x0);
2305 static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev,
2312 rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
2314 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
2318 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12));
2320 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12));
2322 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550);
2325 static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev,
2330 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee);
2332 rtw_bf_remove_bfee_su(rtwdev, bfee);
2335 static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
2340 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
2342 rtw_bf_remove_bfee_mu(rtwdev, bfee);
2345 static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
2349 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
2351 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
2353 rtw_warn(rtwdev, "wrong bfee role\n");
2362 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
2371 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data);
2374 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k)
2376 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2379 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70);
2380 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38);
2381 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1);
2382 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77);
2384 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD,
2386 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control);
2391 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num,
2394 rtw_restore_reg(rtwdev, bckp, reg_num);
2395 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2396 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4);
2400 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg,
2408 bckp[i].val = rtw_read32(rtwdev, reg[i]);
2412 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev,
2419 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A,
2421 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B,
2426 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev,
2433 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK,
2435 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK,
2440 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev)
2442 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2446 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
2454 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path)
2456 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
2458 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801);
2460 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
2463 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path)
2468 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0);
2469 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
2470 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));
2477 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
2478 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
2479 corr_val = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));
2488 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev)
2493 rtw_write8(rtwdev, 0x522, 0xff);
2494 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2);
2497 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000);
2498 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000);
2504 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev)
2506 rtw8822c_dpk_tx_pause(rtwdev);
2507 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl);
2510 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk)
2513 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl);
2515 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl);
2518 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev)
2522 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
2523 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);
2524 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
2525 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G)
2526 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);
2528 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);
2529 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4);
2530 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3);
2532 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2533 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b);
2534 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347);
2537 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path)
2541 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017);
2542 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK);
2544 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
2545 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);
2546 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_TX_OFFSET_VAL, 0x0);
2547 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb);
2549 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) {
2550 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_LB_ATT, 0x1);
2551 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);
2553 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
2554 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6);
2555 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
2556 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0);
2559 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
2560 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
2561 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
2563 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80)
2564 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2);
2566 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
2568 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1);
2575 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path)
2578 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0;
2600 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action)
2605 rtw8822c_dpk_set_gnt_wl(rtwdev, true);
2608 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1);
2609 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0);
2610 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
2612 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) {
2614 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
2617 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
2619 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
2621 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path);
2622 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd);
2623 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1);
2625 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) {
2627 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
2629 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
2631 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
2634 rtw8822c_dpk_set_gnt_wl(rtwdev, false);
2636 rtw_write8(rtwdev, 0x1b10, 0x0);
2641 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path)
2645 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2646 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0);
2648 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
2653 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path)
2655 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
2656 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0);
2657 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
2660 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e);
2663 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path)
2667 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
2668 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
2669 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001);
2670 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
2671 rtw_write32(rtwdev, 0x1b4c, 0x00080000);
2673 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD);
2674 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD);
2681 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
2712 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path)
2716 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2717 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1);
2718 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000);
2720 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0);
2722 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
2727 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path,
2733 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
2734 dgain = rtw8822c_dpk_dgain_read(rtwdev, path);
2744 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path)
2748 loss = rtw8822c_dpk_pas_read(rtwdev, path);
2771 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev,
2776 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN,
2778 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC,
2786 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path,
2801 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev,
2807 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
2809 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0);
2816 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev,
2822 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
2824 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
2831 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev,
2844 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb);
2850 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev,
2853 return rtw8822c_gl_state(rtwdev, data, 1);
2856 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev,
2859 return rtw8822c_gl_state(rtwdev, data, 0);
2862 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev,
2868 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS);
2869 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path);
2874 static u8 (*dpk_state[])(struct rtw_dev *rtwdev,
2880 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path,
2884 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data);
2893 state = func(rtwdev, &data);
2901 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev,
2911 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev)
2916 reg = rtw_read32(rtwdev, REG_STAT_RPT);
2918 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff;
2919 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff;
2935 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path)
2937 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2941 rtw_write32(rtwdev, REG_RXSRAM_CTL,
2943 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev);
2947 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path)
2949 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
2952 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0);
2953 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080);
2955 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1);
2956 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080);
2959 rtw8822c_dpk_coef_tbl_apply(rtwdev, path);
2962 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path)
2964 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2972 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) {
2980 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result)
2982 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2987 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
2988 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
2999 rtw_write32(rtwdev, reg[path] + addr * 4, coef);
3003 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc,
3006 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3008 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3011 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6));
3013 rtw_write8(rtwdev, REG_DPD_AGC, 0x00);
3016 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC);
3018 rtw8822c_dpk_coef_write(rtwdev, path, result);
3021 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path)
3023 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3026 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path);
3027 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC);
3029 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3030 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3031 rtw8822c_dpk_dgain_read(rtwdev, path);
3033 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) {
3034 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3035 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3036 rtw8822c_dpk_dc_corr_check(rtwdev, path);
3039 t1 = rtw8822c_dpk_thermal_read(rtwdev, path);
3040 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true);
3041 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path);
3048 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb);
3052 t2 = rtw8822c_dpk_thermal_read(rtwdev, path);
3059 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path)
3063 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK);
3065 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3067 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26));
3069 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14);
3071 rtw8822c_dpk_get_coef(rtwdev, path);
3076 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path)
3078 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3081 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3082 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0);
3083 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
3084 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
3085 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1);
3086 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3087 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf);
3090 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
3092 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1);
3094 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
3096 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1);
3100 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310);
3101 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310);
3102 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db);
3103 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db);
3104 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3105 rtw_write32(rtwdev, REG_DPD_CTL15,
3108 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c);
3109 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c);
3110 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14);
3111 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14);
3112 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3113 rtw_write32(rtwdev, REG_DPD_CTL15,
3117 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path);
3119 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR);
3121 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0);
3122 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3123 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
3124 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0);
3125 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3128 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b);
3130 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b);
3132 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
3134 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN);
3139 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs);
3141 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs);
3146 static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev)
3148 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3153 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3154 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3155 rtw_write32(rtwdev, REG_NCTL0, 0x00001148);
3156 rtw_write32(rtwdev, REG_NCTL0, 0x00001149);
3158 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55);
3160 rtw_write8(rtwdev, 0x1b10, 0x0);
3161 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3163 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3166 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD,
3168 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3170 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3172 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3174 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path],
3179 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path)
3181 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3183 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
3185 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3186 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
3189 rtw8822c_dpk_cal_gs(rtwdev, path);
3192 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail,
3198 if (rtw8822c_dpk_coef_read(rtwdev, path))
3206 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result);
3211 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev)
3213 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3216 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3218 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3220 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0);
3226 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev,
3231 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path)
3233 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3237 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path);
3239 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path);
3241 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path);
3243 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path))
3244 rtw_err(rtwdev, "failed to do dpk calibration\n");
3246 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path);
3252 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev)
3254 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A);
3255 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B);
3256 rtw8822c_dpk_on(rtwdev, RF_PATH_A);
3257 rtw8822c_dpk_on(rtwdev, RF_PATH_B);
3258 rtw8822c_dpk_cal_coef1(rtwdev);
3261 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev)
3263 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3266 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3268 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN,
3270 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN,
3274 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0);
3275 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]);
3278 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0);
3279 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]);
3283 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev)
3285 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3293 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3294 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3297 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);
3299 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);
3301 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]);
3303 rtw8822c_dpk_coef_write(rtwdev, path,
3306 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
3308 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3311 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
3314 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
3317 rtw8822c_dpk_cal_coef1(rtwdev);
3320 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev)
3322 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3327 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff);
3330 rtw_dbg(rtwdev, RTW_DBG_RFK,
3332 rtw8822c_dpk_reload_data(rtwdev);
3339 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev)
3341 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3353 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n");
3355 } else if (rtw8822c_dpk_reload(rtwdev)) {
3362 rtw8822c_dpk_information(rtwdev);
3364 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp);
3365 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup);
3367 rtw8822c_dpk_mac_bb_setting(rtwdev);
3368 rtw8822c_dpk_afe_setting(rtwdev, true);
3369 rtw8822c_dpk_pre_setting(rtwdev);
3370 rtw8822c_dpk_result_reset(rtwdev);
3371 rtw8822c_dpk_path_select(rtwdev);
3372 rtw8822c_dpk_afe_setting(rtwdev, false);
3373 rtw8822c_dpk_enable_disable(rtwdev);
3375 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup);
3376 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
3377 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3378 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp);
3381 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev)
3383 rtw8822c_do_iqk(rtwdev);
3384 rtw8822c_do_dpk(rtwdev);
3387 static void rtw8822c_dpk_track(struct rtw_dev *rtwdev)
3389 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3398 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path);
3410 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3412 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0),
3436 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev,
3444 pd = rtw_read32_mask(rtwdev,
3447 cs = rtw_read32_mask(rtwdev,
3458 rtw_write32_mask(rtwdev,
3462 rtw_write32_mask(rtwdev,
3468 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
3470 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3476 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000);
3477 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc);
3487 rtw8822c_phy_cck_pd_set_reg(rtwdev,
3495 static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path)
3497 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3501 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK,
3505 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK,
3513 static void rtw8822c_pwr_track_stats(struct rtw_dev *rtwdev, u8 path)
3517 if (rtwdev->efuse.thermal_meter[path] == 0xff)
3520 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e);
3521 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path);
3524 static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev,
3528 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3531 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path);
3533 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path,
3535 rtw8822c_pwrtrack_set(rtwdev, path);
3538 static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev)
3543 rtw_phy_config_swing_table(rtwdev, &swing_table);
3545 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
3546 rtw8822c_pwr_track_stats(rtwdev, i);
3547 if (rtw_phy_pwrtrack_need_lck(rtwdev))
3548 rtw8822c_do_lck(rtwdev);
3549 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
3550 rtw8822c_pwr_track_path(rtwdev, &swing_table, i);
3553 static void rtw8822c_pwr_track(struct rtw_dev *rtwdev)
3555 struct rtw_efuse *efuse = &rtwdev->efuse;
3556 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3562 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
3563 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00);
3564 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
3566 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
3567 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00);
3568 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
3574 __rtw8822c_pwr_track(rtwdev);