Lines Matching refs:hal
149 struct rtw_hal *hal = &rtwdev->hal;
158 for (path = 0; path < hal->rf_path_num; path++) {
536 if (rtwdev->hal.current_band_type != RTW_BAND_2G)
690 struct rtw_hal *hal = &rtwdev->hal;
695 if (rf_path >= hal->rf_phy_num) {
713 struct rtw_hal *hal = &rtwdev->hal;
722 if (rf_path >= hal->rf_phy_num) {
762 struct rtw_hal *hal = &rtwdev->hal;
769 if (rf_path >= hal->rf_phy_num) {
802 struct rtw_hal *hal = &rtwdev->hal;
807 if (rf_path >= hal->rf_phy_num) {
835 struct rtw_hal *hal = &rtwdev->hal;
839 cond.cut = hal->cut_version ? hal->cut_version : 15;
857 hal->phy_cond = cond;
859 rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x\n", *((u32 *)&hal->phy_cond));
864 struct rtw_hal *hal = &rtwdev->hal;
865 struct rtw_phy_cond drv_cond = hal->phy_cond;
1245 struct rtw_hal *hal = &rtwdev->hal;
1265 hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset;
1267 hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset;
1325 struct rtw_hal *hal = &rtwdev->hal;
1343 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit;
1344 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx];
1346 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1348 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit;
1349 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx];
1351 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1360 struct rtw_hal *hal = &rtwdev->hal;
1362 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx];
1363 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx];
1369 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht;
1372 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht;
1512 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) {
1747 struct rtw_hal *hal = &rtwdev->hal;
1748 u8 *cch_by_bw = hal->cch_by_bw;
1790 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] :
1791 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx];
1807 struct rtw_hal *hal = &rtwdev->hal;
1825 *offset = hal->tx_pwr_by_rate_offset_2g[path][rate];
1831 *offset = hal->tx_pwr_by_rate_offset_5g[path][rate];
1869 struct rtw_hal *hal = &rtwdev->hal;
1883 bw = hal->current_band_width;
1888 hal->tx_pwr_tbl[path][rate] = pwr_idx;
1900 struct rtw_hal *hal = &rtwdev->hal;
1904 if (hal->current_band_type == RTW_BAND_2G)
1916 struct rtw_hal *hal = &rtwdev->hal;
1919 mutex_lock(&hal->tx_power_mutex);
1921 for (path = 0; path < hal->rf_path_num; path++)
1925 mutex_unlock(&hal->tx_power_mutex);
1930 rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path,
1941 base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx];
1942 base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx];
1943 hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g;
1944 hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g;
1947 hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g;
1948 hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g;
1952 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal)
1957 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1960 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1963 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1966 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1969 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1972 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1979 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs)
1985 base = hal->tx_pwr_by_rate_base_2g[0][rs];
1986 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base;
1990 base = hal->tx_pwr_by_rate_base_5g[0][rs];
1991 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base;
1995 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal)
2000 hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1;
2005 __rtw_phy_tx_power_limit_config(hal, regd, bw, rs);
2011 struct rtw_hal *hal = &rtwdev->hal;
2017 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index;
2021 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index;
2026 struct rtw_hal *hal = &rtwdev->hal;
2032 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0;
2033 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0;
2049 u8 channel = rtwdev->hal.current_channel;