Lines Matching refs:rtwdev
11 void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw,
25 rtw_write8(rtwdev, REG_DATA_SC,
28 value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL);
41 rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32);
43 if (rtw_chip_wcpu_11n(rtwdev))
46 value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL);
48 rtw_write32(rtwdev, REG_AFE_CTRL1, value32);
50 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
51 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
53 value8 = rtw_read8(rtwdev, REG_CCK_CHECK);
57 rtw_write8(rtwdev, REG_CCK_CHECK, value8);
61 static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev)
66 rtw_write8(rtwdev, REG_RSV_CTRL, 0);
68 if (rtw_chip_wcpu_11n(rtwdev)) {
69 if (rtw_read32(rtwdev, REG_SYS_CFG1) & BIT_LDO)
70 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, LDO_SEL);
72 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, SPS_SEL);
76 switch (rtw_hci_type(rtwdev)) {
78 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_BT_DIG_CLK_EN);
87 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1);
89 rtw_write32(rtwdev, REG_PAD_CTRL1, value32);
91 value32 = rtw_read32(rtwdev, REG_LED_CFG);
93 rtw_write32(rtwdev, REG_LED_CFG, value32);
95 value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG);
97 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32);
100 value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
102 rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8);
104 value8 = rtw_read8(rtwdev, REG_RF_CTRL);
106 rtw_write8(rtwdev, REG_RF_CTRL, value8);
108 value32 = rtw_read32(rtwdev, REG_WLRF1);
110 rtw_write32(rtwdev, REG_WLRF1, value32);
115 static bool do_pwr_poll_cmd(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target)
123 rtwdev, addr) == 0;
126 static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev,
137 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
140 if (rtw_hci_type(rtwdev) != RTW_HCI_TYPE_PCIE)
144 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL);
145 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
146 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
147 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
148 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
149 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
150 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
152 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
156 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n",
161 static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask,
181 value = rtw_read8(rtwdev, offset);
184 rtw_write8(rtwdev, offset, value);
187 if (rtw_pwr_cmd_polling(rtwdev, cur_cmd))
206 static int rtw_pwr_seq_parser(struct rtw_dev *rtwdev,
216 cut = rtwdev->hal.cut_version;
218 switch (rtw_hci_type(rtwdev)) {
234 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd);
244 static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on)
246 struct rtw_chip_info *chip = rtwdev->chip;
252 if (rtw_chip_wcpu_11ac(rtwdev)) {
253 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr);
256 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) {
258 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm);
262 if (rtw_read8(rtwdev, REG_CR) == 0xea)
264 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
265 (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0)))
274 ret = rtw_pwr_seq_parser(rtwdev, pwr_seq);
281 static int __rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
283 u8 sys_func_en = rtwdev->chip->sys_func_en;
287 value = rtw_read32(rtwdev, REG_CPU_DMEM_CON);
289 rtw_write32(rtwdev, REG_CPU_DMEM_CON, value);
291 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en);
292 value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C;
293 rtw_write8(rtwdev, REG_CR_EXT + 3, value8);
296 tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL);
298 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
299 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
300 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value);
306 static int __rtw_mac_init_system_cfg_legacy(struct rtw_dev *rtwdev)
308 rtw_write8(rtwdev, REG_CR, 0xff);
310 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f);
313 rtw_write8_set(rtwdev, REG_SYS_CLKR, BIT_WAKEPAD_EN);
314 rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC);
316 rtw_write16(rtwdev, REG_CR, 0x2ff);
321 static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
323 if (rtw_chip_wcpu_11n(rtwdev))
324 return __rtw_mac_init_system_cfg_legacy(rtwdev);
326 return __rtw_mac_init_system_cfg(rtwdev);
329 int rtw_mac_power_on(struct rtw_dev *rtwdev)
333 ret = rtw_mac_pre_system_cfg(rtwdev);
337 ret = rtw_mac_power_switch(rtwdev, true);
339 rtw_mac_power_switch(rtwdev, false);
340 ret = rtw_mac_power_switch(rtwdev, true);
347 ret = rtw_mac_init_system_cfg(rtwdev);
354 rtw_err(rtwdev, "mac power on failed");
358 void rtw_mac_power_off(struct rtw_dev *rtwdev)
360 rtw_mac_power_switch(rtwdev, false);
386 static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable)
390 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
393 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
396 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
399 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
405 static void download_firmware_reg_backup(struct rtw_dev *rtwdev,
414 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1);
417 rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp);
422 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR);
429 rtw_write8(rtwdev, REG_CR, tmp);
430 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
435 bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1);
439 bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN;
441 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200);
442 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val);
445 tmp = rtw_read8(rtwdev, REG_BCN_CTRL);
451 rtw_write8(rtwdev, REG_BCN_CTRL, tmp);
456 static void download_firmware_reset_platform(struct rtw_dev *rtwdev)
458 rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
459 rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
460 rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
461 rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
464 static void download_firmware_reg_restore(struct rtw_dev *rtwdev,
468 rtw_restore_reg(rtwdev, bckp, bckp_num);
473 static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
483 ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size);
489 send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size)
493 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
497 ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size);
499 rtw_err(rtwdev, "failed to download rsvd page\n");
505 iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl)
507 rtw_write32(rtwdev, REG_DDMA_CH0SA, src);
508 rtw_write32(rtwdev, REG_DDMA_CH0DA, dst);
509 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl);
511 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
517 static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst,
522 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
529 if (iddma_enable(rtwdev, src, dst, ch0_ctrl))
536 check_fw_checksum(struct rtw_dev *rtwdev, u32 addr)
540 fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL);
542 if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) {
546 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
550 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
553 rtw_err(rtwdev, "invalid fw checksum\n");
560 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
563 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
570 download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data,
573 struct rtw_chip_info *chip = rtwdev->chip;
587 val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL);
589 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val);
597 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7),
602 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX +
614 if (!check_fw_checksum(rtwdev, dst))
621 start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size)
640 val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800);
642 rtw_write16(rtwdev, REG_MCUFW_CTRL, val);
647 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size);
654 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size);
662 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr,
671 static int download_firmware_validate(struct rtw_dev *rtwdev)
675 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) {
676 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK;
678 rtw_err(rtwdev, "invalid fw key\n");
685 static void download_firmware_end_flow(struct rtw_dev *rtwdev)
689 rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF);
692 fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL);
697 rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
700 static int __rtw_download_firmware(struct rtw_dev *rtwdev,
712 if (!ltecoex_read_reg(rtwdev, 0x38, <ecoex_bckp))
715 wlan_cpu_enable(rtwdev, false);
717 download_firmware_reg_backup(rtwdev, bckp);
718 download_firmware_reset_platform(rtwdev);
720 ret = start_download_firmware(rtwdev, data, size);
724 download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM);
726 download_firmware_end_flow(rtwdev);
728 wlan_cpu_enable(rtwdev, true);
730 if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp))
733 ret = download_firmware_validate(rtwdev);
738 rtw_hci_setup(rtwdev);
740 rtwdev->h2c.last_box_num = 0;
741 rtwdev->h2c.seq = 0;
743 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
749 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
750 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
755 static void en_download_firmware_legacy(struct rtw_dev *rtwdev, bool en)
760 wlan_cpu_enable(rtwdev, false);
761 wlan_cpu_enable(rtwdev, true);
763 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
766 if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN)
768 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
771 rtw_err(rtwdev, "failed to check fw download ready\n");
773 rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN);
775 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
780 write_firmware_page(struct rtw_dev *rtwdev, u32 page, const u8 *data, u32 size)
793 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
796 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32);
799 rtw_write32(rtwdev, write_addr, le32_to_cpu(*ptr));
807 rtw_write32(rtwdev, write_addr, le32_to_cpu(remain_data));
812 download_firmware_legacy(struct rtw_dev *rtwdev, const u8 *data, u32 size)
824 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT);
827 write_firmware_page(rtwdev, page, data, DLFW_PAGE_SIZE_LEGACY);
831 write_firmware_page(rtwdev, page, data, last_page_size);
833 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) {
834 rtw_err(rtwdev, "failed to check download firmware report\n");
841 static int download_firmware_validate_legacy(struct rtw_dev *rtwdev)
846 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
849 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32);
851 wlan_cpu_enable(rtwdev, false);
852 wlan_cpu_enable(rtwdev, true);
855 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
861 rtw_err(rtwdev, "failed to validate firmware\n");
865 static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev,
870 en_download_firmware_legacy(rtwdev, true);
871 ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size);
872 en_download_firmware_legacy(rtwdev, false);
876 ret = download_firmware_validate_legacy(rtwdev);
881 rtw_hci_setup(rtwdev);
883 rtwdev->h2c.last_box_num = 0;
884 rtwdev->h2c.seq = 0;
886 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
892 int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw)
894 if (rtw_chip_wcpu_11n(rtwdev))
895 return __rtw_download_firmware_legacy(rtwdev, fw);
897 return __rtw_download_firmware(rtwdev, fw);
900 static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues)
902 const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn;
917 static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev,
920 struct rtw_chip_info *chip = rtwdev->chip;
934 rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) :
935 rtw_read8(rtwdev, addr->rsvd);
936 avail_page = wsize ? rtw_read16(rtwdev, addr->avail) :
937 rtw_read8(rtwdev, addr->avail);
951 rtw_warn(rtwdev, "timed out to flush queue %d\n", prio_queue);
954 static void rtw_mac_flush_prio_queues(struct rtw_dev *rtwdev,
961 __rtw_mac_flush_prio_queue(rtwdev, q, drop);
964 void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop)
972 if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn)
975 prio_queues = get_priority_queues(rtwdev, queues);
977 rtw_mac_flush_prio_queues(rtwdev, prio_queues, drop);
980 static int txdma_queue_mapping(struct rtw_dev *rtwdev)
982 struct rtw_chip_info *chip = rtwdev->chip;
986 switch (rtw_hci_type(rtwdev)) {
991 if (rtwdev->hci.bulkout_num == 2)
993 else if (rtwdev->hci.bulkout_num == 3)
995 else if (rtwdev->hci.bulkout_num == 4)
1004 rtwdev->fifo.rqpn = rqpn;
1011 rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map);
1013 rtw_write8(rtwdev, REG_CR, 0);
1014 rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE);
1015 if (rtw_chip_wcpu_11ac(rtwdev))
1016 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
1021 static int set_trx_fifo_info(struct rtw_dev *rtwdev)
1023 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1024 struct rtw_chip_info *chip = rtwdev->chip;
1031 if (rtw_chip_wcpu_11n(rtwdev))
1049 if (rtw_chip_wcpu_11ac(rtwdev)) {
1067 rtw_err(rtwdev, "wrong rsvd driver address\n");
1074 static int __priority_queue_cfg(struct rtw_dev *rtwdev,
1078 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1079 struct rtw_chip_info *chip = rtwdev->chip;
1081 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num);
1082 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num);
1083 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num);
1084 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num);
1085 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num);
1086 rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN);
1088 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary);
1089 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16);
1091 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary);
1092 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary);
1093 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary);
1094 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
1095 rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
1097 if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0))
1100 rtw_write8(rtwdev, REG_CR + 3, 0);
1105 static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev,
1109 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1110 struct rtw_chip_info *chip = rtwdev->chip;
1114 rtw_write32(rtwdev, REG_RQPN_NPQ, val32);
1116 rtw_write32(rtwdev, REG_RQPN, val32);
1118 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary);
1119 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1);
1120 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary);
1121 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary);
1122 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary);
1123 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary);
1125 rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT);
1127 if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0))
1133 static int priority_queue_cfg(struct rtw_dev *rtwdev)
1135 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1136 struct rtw_chip_info *chip = rtwdev->chip;
1141 ret = set_trx_fifo_info(rtwdev);
1145 switch (rtw_hci_type(rtwdev)) {
1150 if (rtwdev->hci.bulkout_num == 2)
1152 else if (rtwdev->hci.bulkout_num == 3)
1154 else if (rtwdev->hci.bulkout_num == 4)
1165 if (rtw_chip_wcpu_11n(rtwdev))
1166 return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num);
1168 return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num);
1171 static int init_h2c(struct rtw_dev *rtwdev)
1173 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1181 if (rtw_chip_wcpu_11n(rtwdev))
1187 value32 = rtw_read32(rtwdev, REG_H2C_HEAD);
1189 rtw_write32(rtwdev, REG_H2C_HEAD, value32);
1191 value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR);
1193 rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32);
1195 value32 = rtw_read32(rtwdev, REG_H2C_TAIL);
1198 rtw_write32(rtwdev, REG_H2C_TAIL, value32);
1200 value8 = rtw_read8(rtwdev, REG_H2C_INFO);
1202 rtw_write8(rtwdev, REG_H2C_INFO, value8);
1204 value8 = rtw_read8(rtwdev, REG_H2C_INFO);
1206 rtw_write8(rtwdev, REG_H2C_INFO, value8);
1208 value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1);
1210 rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8);
1212 wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF;
1213 rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF;
1217 rtw_err(rtwdev, "H2C queue mismatch\n");
1224 static int rtw_init_trx_cfg(struct rtw_dev *rtwdev)
1228 ret = txdma_queue_mapping(rtwdev);
1232 ret = priority_queue_cfg(rtwdev);
1236 ret = init_h2c(rtwdev);
1243 static int rtw_drv_info_cfg(struct rtw_dev *rtwdev)
1247 rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE);
1248 if (rtw_chip_wcpu_11ac(rtwdev)) {
1249 value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1);
1253 rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8);
1255 rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS);
1256 rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9));
1261 int rtw_mac_init(struct rtw_dev *rtwdev)
1263 struct rtw_chip_info *chip = rtwdev->chip;
1266 ret = rtw_init_trx_cfg(rtwdev);
1270 ret = chip->ops->mac_init(rtwdev);
1274 ret = rtw_drv_info_cfg(rtwdev);
1278 rtw_hci_interface_cfg(rtwdev);