Lines Matching defs:value
129 u8 value;
137 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
144 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL);
146 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
147 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
148 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
150 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
152 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
156 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n",
157 offset, cmd->mask, cmd->value);
167 u8 value;
181 value = rtw_read8(rtwdev, offset);
182 value &= ~cur_cmd->mask;
183 value |= (cur_cmd->value & cur_cmd->mask);
184 rtw_write8(rtwdev, offset, value);
191 if (cur_cmd->value == RTW_PWR_DELAY_US)
285 u32 value, tmp;
287 value = rtw_read32(rtwdev, REG_CPU_DMEM_CON);
288 value |= BIT_WL_PLATFORM_RST | BIT_DDMA_EN;
289 rtw_write32(rtwdev, REG_CPU_DMEM_CON, value);
299 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
300 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value);