Lines Matching defs:rtlpriv
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
155 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
198 struct rtl_priv *rtlpriv = rtl_priv(hw);
212 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
240 struct rtl_priv *rtlpriv = rtl_priv(hw);
252 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
301 struct rtl_priv *rtlpriv = rtl_priv(hw);
307 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
308 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
311 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
314 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
330 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
342 struct rtl_priv *rtlpriv = rtl_priv(hw);
352 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
379 struct rtl_priv *rtlpriv = rtl_priv(hw);
381 rtlpriv->io.dev = dev;
383 rtlpriv->io.write8_async = pci_write8_async;
384 rtlpriv->io.write16_async = pci_write16_async;
385 rtlpriv->io.write32_async = pci_write32_async;
387 rtlpriv->io.read8_sync = pci_read8_sync;
388 rtlpriv->io.read16_sync = pci_read16_sync;
389 rtlpriv->io.read32_sync = pci_read32_sync;
396 struct rtl_priv *rtlpriv = rtl_priv(hw);
408 spin_lock_bh(&rtlpriv->locks.waitq_lock);
409 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
421 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
428 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
436 struct rtl_priv *rtlpriv = rtl_priv(hw);
444 if (!rtlpriv->rtlhal.earlymode_enable)
447 if (rtlpriv->dm.supp_phymode_switch &&
448 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
449 (rtlpriv->buddy_priv &&
450 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
458 rtlpriv->psc.rfpwr_state == ERFON) {
463 spin_lock(&rtlpriv->locks.waitq_lock);
469 spin_unlock(&rtlpriv->locks.waitq_lock);
472 spin_unlock(&rtlpriv->locks.waitq_lock);
482 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
489 struct rtl_priv *rtlpriv = rtl_priv(hw);
501 if (rtlpriv->use_new_trx_flow)
506 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
512 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
517 if (rtlpriv->rtlhal.earlymode_enable)
520 rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
538 rtlpriv->mac80211.offchan_delay = true;
539 rtlpriv->psc.state_inap = true;
541 rtlpriv->psc.state_inap = false;
557 rtlpriv->link_info.tidtx_inperiod[tid]++;
571 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
582 if (((rtlpriv->link_info.num_rx_inperiod +
583 rtlpriv->link_info.num_tx_inperiod) > 8) ||
584 rtlpriv->link_info.num_rx_inperiod > 2)
592 struct rtl_priv *rtlpriv = rtl_priv(hw);
615 if (rtlpriv->use_new_trx_flow) {
617 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
621 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
624 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
627 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
672 struct rtl_priv *rtlpriv = rtl_priv(hw);
675 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
676 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
682 struct rtl_priv *rtlpriv = rtl_priv(hw);
711 if (rtlpriv->use_new_trx_flow) {
714 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
725 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
744 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
747 if (rtlpriv->use_new_trx_flow)
748 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
752 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
757 if (rtlpriv->use_new_trx_flow)
764 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
795 rtlpriv->stats.rxbytesunicast += skb->len;
800 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
802 rtlpriv->link_info.num_rx_inperiod++;
813 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
814 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
826 if (rtlpriv->use_new_trx_flow) {
832 rtl_write_word(rtlpriv, 0x3B4,
835 if (((rtlpriv->link_info.num_rx_inperiod +
836 rtlpriv->link_info.num_tx_inperiod) > 8) ||
837 rtlpriv->link_info.num_rx_inperiod > 2)
841 if (rtlpriv->use_new_trx_flow) {
851 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
866 struct rtl_priv *rtlpriv = rtl_priv(hw);
876 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
877 rtlpriv->cfg->ops->disable_interrupt(hw);
880 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
887 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
888 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
891 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
892 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
895 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
896 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
898 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
899 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
901 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
905 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
906 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
908 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
909 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
914 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
915 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
920 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
921 rtlpriv->link_info.num_tx_inperiod++;
923 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
928 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
929 rtlpriv->link_info.num_tx_inperiod++;
931 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
936 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
937 rtlpriv->link_info.num_tx_inperiod++;
939 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
944 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
945 rtlpriv->link_info.num_tx_inperiod++;
947 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
953 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
954 rtlpriv->link_info.num_tx_inperiod++;
956 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
963 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
964 rtlpriv->link_info.num_tx_inperiod++;
966 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
973 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
974 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
978 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
979 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
984 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
985 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
991 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
992 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
994 queue_delayed_work(rtlpriv->works.rtl_wq,
995 &rtlpriv->works.fwevt_wq, 0);
1008 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1009 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1015 if (rtlpriv->rtlhal.earlymode_enable)
1016 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1019 rtlpriv->cfg->ops->enable_interrupt(hw);
1020 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1026 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet);
1027 struct ieee80211_hw *hw = rtlpriv->hw;
1033 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t,
1035 struct ieee80211_hw *hw = rtlpriv->hw;
1052 if (rtlpriv->use_new_trx_flow)
1058 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1071 if (rtlpriv->use_new_trx_flow)
1074 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1080 if (rtlpriv->use_new_trx_flow) {
1082 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1085 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1093 struct rtl_priv *rtlpriv = rtl_priv(hw);
1094 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1127 struct rtl_priv *rtlpriv = rtl_priv(hw);
1159 tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet);
1160 tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet,
1162 INIT_WORK(&rtlpriv->works.lps_change_work,
1170 struct rtl_priv *rtlpriv = rtl_priv(hw);
1178 if (rtlpriv->use_new_trx_flow) {
1213 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1217 if (!rtlpriv->use_new_trx_flow) {
1223 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1235 struct rtl_priv *rtlpriv = rtl_priv(hw);
1238 if (rtlpriv->use_new_trx_flow) {
1285 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1294 struct rtl_priv *rtlpriv = rtl_priv(hw);
1303 if (rtlpriv->use_new_trx_flow)
1309 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1321 if (rtlpriv->use_new_trx_flow) {
1331 struct rtl_priv *rtlpriv = rtl_priv(hw);
1347 if (rtlpriv->use_new_trx_flow) {
1416 struct rtl_priv *rtlpriv = rtl_priv(hw);
1429 if (!rtlpriv->use_new_trx_flow &&
1437 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1442 if (rtlpriv->use_new_trx_flow) {
1443 rtlpriv->cfg->ops->set_desc(hw,
1448 rtlpriv->cfg->ops->set_desc(hw,
1452 rtlpriv->cfg->ops->set_desc(hw,
1456 rtlpriv->cfg->ops->set_desc(hw,
1462 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1471 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1481 if (rtlpriv->use_new_trx_flow)
1488 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1495 if (rtlpriv->use_new_trx_flow) {
1504 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1513 struct rtl_priv *rtlpriv = rtl_priv(hw);
1522 if (!rtlpriv->rtlhal.earlymode_enable)
1538 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1541 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1542 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1543 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1553 struct rtl_priv *rtlpriv = rtl_priv(hw);
1571 if (rtlpriv->psc.sw_ps_enabled) {
1580 rtlpriv->stats.txbytesmulticast += skb->len;
1582 rtlpriv->stats.txbytesbroadcast += skb->len;
1584 rtlpriv->stats.txbytesunicast += skb->len;
1586 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1589 if (rtlpriv->use_new_trx_flow)
1599 if (rtlpriv->use_new_trx_flow) {
1602 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1606 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1611 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1617 if (rtlpriv->cfg->ops->get_available_desc &&
1618 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1619 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1621 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1626 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1628 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1633 if (rtlpriv->use_new_trx_flow) {
1634 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1637 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1643 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1651 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1653 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1660 struct rtl_priv *rtlpriv = rtl_priv(hw);
1690 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1698 struct rtl_priv *rtlpriv = rtl_priv(hw);
1704 tasklet_kill(&rtlpriv->works.irq_tasklet);
1705 cancel_work_sync(&rtlpriv->works.lps_change_work);
1707 flush_workqueue(rtlpriv->works.rtl_wq);
1708 destroy_workqueue(rtlpriv->works.rtl_wq);
1728 struct rtl_priv *rtlpriv = rtl_priv(hw);
1733 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1740 if (rtlpriv->cfg->ops->get_btc_status &&
1741 rtlpriv->cfg->ops->get_btc_status()) {
1742 rtlpriv->btcoexist.btc_info.ap_num = 36;
1743 btc_ops->btc_init_variables(rtlpriv);
1744 btc_ops->btc_init_hal_vars(rtlpriv);
1746 btc_ops->btc_init_variables_wifi_only(rtlpriv);
1749 err = rtlpriv->cfg->ops->hw_init(hw);
1751 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1753 kfree(rtlpriv->btcoexist.btc_context);
1754 kfree(rtlpriv->btcoexist.wifi_only_context);
1757 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1760 rtlpriv->cfg->ops->enable_interrupt(hw);
1761 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1772 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1778 struct rtl_priv *rtlpriv = rtl_priv(hw);
1785 if (rtlpriv->cfg->ops->get_btc_status())
1786 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1788 if (rtlpriv->btcoexist.btc_ops)
1789 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1797 rtlpriv->cfg->ops->disable_interrupt(hw);
1798 cancel_work_sync(&rtlpriv->works.lps_change_work);
1800 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1802 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1804 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1809 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1812 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1814 rtlpriv->cfg->ops->hw_disable(hw);
1816 if (!rtlpriv->max_fw_size)
1818 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1820 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1822 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1830 struct rtl_priv *rtlpriv = rtl_priv(hw);
1866 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1872 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1878 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1886 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1894 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1900 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1905 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1909 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1913 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1917 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1921 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1926 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1929 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1939 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1943 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1948 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1959 rtlpriv->use_new_trx_flow = true;
1963 rtlpriv->use_new_trx_flow = false;
1983 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2007 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2014 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2023 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2030 struct rtl_priv *rtlpriv = rtl_priv(hw);
2048 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2055 struct rtl_priv *rtlpriv = rtl_priv(hw);
2066 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2107 struct rtl_priv *rtlpriv = NULL;
2155 rtlpriv = hw->priv;
2156 rtlpriv->hw = hw;
2157 pcipriv = (void *)rtlpriv->priv;
2159 init_completion(&rtlpriv->firmware_loading_complete);
2161 rtlpriv->proximity.proxim_on = false;
2163 pcipriv = (void *)rtlpriv->priv;
2167 rtlpriv->rtlhal.interface = INTF_PCI;
2168 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2169 rtlpriv->intf_ops = &rtl_pci_ops;
2170 rtlpriv->glb_var = &rtl_global_var;
2180 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2181 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2182 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2185 rtlpriv->io.pci_mem_start =
2187 rtlpriv->cfg->bar_id, pmem_len);
2188 if (rtlpriv->io.pci_mem_start == 0) {
2194 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2197 rtlpriv->io.pci_mem_start);
2216 rtlpriv->cfg->ops->read_eeprom_info(hw);
2218 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2223 rtlpriv->cfg->ops->init_sw_leds(hw);
2248 rtlpriv->mac80211.mac80211_registered = 1;
2259 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2266 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2274 if (rtlpriv->io.pci_mem_start != 0)
2275 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2278 complete(&rtlpriv->firmware_loading_complete);
2293 struct rtl_priv *rtlpriv = rtl_priv(hw);
2295 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2298 wait_for_completion(&rtlpriv->firmware_loading_complete);
2299 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2310 rtlpriv->intf_ops->adapter_stop(hw);
2312 rtlpriv->cfg->ops->disable_interrupt(hw);
2319 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2329 list_del(&rtlpriv->list);
2330 if (rtlpriv->io.pci_mem_start != 0) {
2331 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2364 struct rtl_priv *rtlpriv = rtl_priv(hw);
2366 rtlpriv->cfg->ops->hw_suspend(hw);
2376 struct rtl_priv *rtlpriv = rtl_priv(hw);
2378 rtlpriv->cfg->ops->hw_resume(hw);