Lines Matching refs:rt2x00dev
29 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
39 idx = rt2x00mmio_register_read(rt2x00dev, TX_DTX_IDX(qid));
42 idx = rt2x00mmio_register_read(rt2x00dev, TX_DTX_IDX(5));
189 static void rt2800mmio_wakeup(struct rt2x00_dev *rt2x00dev)
194 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
197 static inline void rt2800mmio_enable_interrupt(struct rt2x00_dev *rt2x00dev,
206 spin_lock_irq(&rt2x00dev->irqmask_lock);
207 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR);
209 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
210 spin_unlock_irq(&rt2x00dev->irqmask_lock);
215 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
217 rt2x00lib_pretbtt(rt2x00dev);
218 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
219 rt2800mmio_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
225 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet);
226 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
229 rt2x00lib_beacondone(rt2x00dev);
231 if (rt2x00dev->intf_ap_count) {
239 reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);
241 (rt2x00dev->beacon_int * 16) - 1);
242 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
244 reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);
246 (rt2x00dev->beacon_int * 16));
247 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
253 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
254 rt2800mmio_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
260 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
262 if (rt2x00mmio_rxdone(rt2x00dev))
263 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
264 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
265 rt2800mmio_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
271 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
273 rt2800mmio_wakeup(rt2x00dev);
274 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
275 rt2800mmio_enable_interrupt(rt2x00dev,
280 static void rt2800mmio_fetch_txstatus(struct rt2x00_dev *rt2x00dev)
300 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
302 while (!kfifo_is_full(&rt2x00dev->txstatus_fifo)) {
303 status = rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO);
307 kfifo_put(&rt2x00dev->txstatus_fifo, status);
310 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
315 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
318 rt2800_txdone(rt2x00dev, 16);
320 if (!kfifo_is_empty(&rt2x00dev->txstatus_fifo))
321 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
328 struct rt2x00_dev *rt2x00dev = dev_instance;
332 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR);
333 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
338 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
350 rt2800mmio_fetch_txstatus(rt2x00dev);
351 if (!kfifo_is_empty(&rt2x00dev->txstatus_fifo))
352 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
356 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
359 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
362 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
365 tasklet_schedule(&rt2x00dev->autowake_tasklet);
371 spin_lock(&rt2x00dev->irqmask_lock);
372 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR);
374 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
375 spin_unlock(&rt2x00dev->irqmask_lock);
381 void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev,
392 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR);
393 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
396 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
405 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
406 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
412 tasklet_kill(&rt2x00dev->txstatus_tasklet);
413 tasklet_kill(&rt2x00dev->rxdone_tasklet);
414 tasklet_kill(&rt2x00dev->autowake_tasklet);
415 tasklet_kill(&rt2x00dev->tbtt_tasklet);
416 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
426 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
431 reg = rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL);
433 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
436 reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);
440 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
442 reg = rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN);
444 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
457 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
467 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
469 hrtimer_start(&rt2x00dev->txstatus_timer,
474 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(5),
485 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
516 queue_work(rt2x00dev->workqueue, &rt2x00dev->txdone_work);
529 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
534 reg = rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL);
536 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
539 reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);
543 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
545 reg = rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN);
547 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
554 tasklet_kill(&rt2x00dev->tbtt_tasklet);
555 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
566 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
569 rt2800_get_txwi_rxwi_size(rt2x00dev, &txwi_size, &rxwi_size);
631 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
647 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
656 hrtimer_cancel(&rt2x00dev->txstatus_timer);
661 int rt2800mmio_init_queues(struct rt2x00_dev *rt2x00dev)
668 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
669 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0,
671 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0,
672 rt2x00dev->tx[0].limit);
673 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0);
674 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0);
676 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
677 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1,
679 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1,
680 rt2x00dev->tx[1].limit);
681 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0);
682 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0);
684 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
685 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2,
687 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2,
688 rt2x00dev->tx[2].limit);
689 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0);
690 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0);
692 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
693 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3,
695 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3,
696 rt2x00dev->tx[3].limit);
697 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0);
698 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0);
700 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0);
701 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0);
702 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0);
703 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0);
705 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0);
706 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0);
707 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0);
708 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0);
710 entry_priv = rt2x00dev->rx->entries[0].priv_data;
711 rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR,
713 rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT,
714 rt2x00dev->rx[0].limit);
715 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
716 rt2x00dev->rx[0].limit - 1);
717 rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0);
719 rt2800_disable_wpdma(rt2x00dev);
721 rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0);
727 int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev)
734 reg = rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX);
742 rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
744 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
745 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
747 if (rt2x00_is_pcie(rt2x00dev) &&
748 (rt2x00_rt(rt2x00dev, RT3090) ||
749 rt2x00_rt(rt2x00dev, RT3390) ||
750 rt2x00_rt(rt2x00dev, RT3572) ||
751 rt2x00_rt(rt2x00dev, RT3593) ||
752 rt2x00_rt(rt2x00dev, RT5390) ||
753 rt2x00_rt(rt2x00dev, RT5392) ||
754 rt2x00_rt(rt2x00dev, RT5592))) {
755 reg = rt2x00mmio_register_read(rt2x00dev, AUX_CTRL);
758 rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
761 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
766 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
768 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
777 int rt2800mmio_enable_radio(struct rt2x00_dev *rt2x00dev)
780 rt2800_wait_wpdma_ready(rt2x00dev);
782 if (unlikely(rt2800mmio_init_queues(rt2x00dev)))
785 return rt2800_enable_radio(rt2x00dev);
791 struct rt2x00_dev *rt2x00dev =
794 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
797 while (!kfifo_is_empty(&rt2x00dev->txstatus_fifo) ||
798 rt2800_txstatus_timeout(rt2x00dev)) {
800 tasklet_disable(&rt2x00dev->txstatus_tasklet);
801 rt2800_txdone(rt2x00dev, UINT_MAX);
802 rt2800_txdone_nostatus(rt2x00dev);
803 tasklet_enable(&rt2x00dev->txstatus_tasklet);
806 if (rt2800_txstatus_pending(rt2x00dev))
807 hrtimer_start(&rt2x00dev->txstatus_timer,
813 struct rt2x00_dev *rt2x00dev =
816 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
819 if (!rt2800_txstatus_pending(rt2x00dev))
822 rt2800mmio_fetch_txstatus(rt2x00dev);
823 if (!kfifo_is_empty(&rt2x00dev->txstatus_fifo))
824 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
826 queue_work(rt2x00dev->workqueue, &rt2x00dev->txdone_work);
831 int rt2800mmio_probe_hw(struct rt2x00_dev *rt2x00dev)
835 retval = rt2800_probe_hw(rt2x00dev);
842 rt2x00dev->txstatus_timer.function = rt2800mmio_tx_sta_fifo_timeout;
847 INIT_WORK(&rt2x00dev->txdone_work, rt2800mmio_work_txdone);