Lines Matching refs:rt2x00dev
64 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
67 if (!rt2x00_is_soc(rt2x00dev) ||
68 !rt2x00_rt(rt2x00dev, RT2872))
72 if (rt2x00_rf(rt2x00dev, RF3020) ||
73 rt2x00_rf(rt2x00dev, RF3021) ||
74 rt2x00_rf(rt2x00dev, RF3022))
77 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
81 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
86 mutex_lock(&rt2x00dev->csr_mutex);
92 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
100 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
103 mutex_unlock(&rt2x00dev->csr_mutex);
106 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
111 mutex_lock(&rt2x00dev->csr_mutex);
121 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
128 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
130 WAIT_FOR_BBP(rt2x00dev, ®);
135 mutex_unlock(&rt2x00dev->csr_mutex);
140 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 mutex_lock(&rt2x00dev->csr_mutex);
151 switch (rt2x00dev->chip.rt) {
153 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) {
161 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
166 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
173 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
178 mutex_unlock(&rt2x00dev->csr_mutex);
181 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
184 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
187 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
190 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
191 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
194 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
197 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
198 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
201 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
207 mutex_lock(&rt2x00dev->csr_mutex);
217 switch (rt2x00dev->chip.rt) {
219 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) {
226 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
228 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®);
235 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
241 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
243 WAIT_FOR_RFCSR(rt2x00dev, ®);
250 mutex_unlock(&rt2x00dev->csr_mutex);
255 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
258 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
261 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
266 mutex_lock(&rt2x00dev->csr_mutex);
272 if (WAIT_FOR_RF(rt2x00dev, ®)) {
279 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
280 rt2x00_rf_write(rt2x00dev, word, value);
283 mutex_unlock(&rt2x00dev->csr_mutex);
366 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
374 wiphy_name(rt2x00dev->hw->wiphy), word))
377 if (rt2x00_rt(rt2x00dev, RT3593) ||
378 rt2x00_rt(rt2x00dev, RT3883))
393 wiphy_name(rt2x00dev->hw->wiphy), word);
398 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
403 index = rt2800_eeprom_word_index(rt2x00dev, word);
404 return rt2x00_eeprom_addr(rt2x00dev, index);
407 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
412 index = rt2800_eeprom_word_index(rt2x00dev, word);
413 return rt2x00_eeprom_read(rt2x00dev, index);
416 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
421 index = rt2800_eeprom_word_index(rt2x00dev, word);
422 rt2x00_eeprom_write(rt2x00dev, index, data);
425 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
431 index = rt2800_eeprom_word_index(rt2x00dev, array);
432 return rt2x00_eeprom_read(rt2x00dev, index + offset);
435 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
440 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
445 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
455 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
467 rt2800_register_write(rt2x00dev, 0x58, 0x018);
469 rt2800_register_write(rt2x00dev, 0x58, 0x418);
471 rt2800_register_write(rt2x00dev, 0x58, 0x618);
478 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
482 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
485 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
487 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
493 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
502 if (rt2x00_is_soc(rt2x00dev))
505 mutex_lock(&rt2x00dev->csr_mutex);
511 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
516 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
520 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
523 mutex_unlock(&rt2x00dev->csr_mutex);
527 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
533 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
539 rt2x00_err(rt2x00dev, "Unstable hardware\n");
544 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
554 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
562 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
567 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
571 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
577 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
581 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
585 switch (rt2x00dev->chip.rt) {
638 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
654 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
670 if (rt2x00_is_usb(rt2x00dev) &&
671 !rt2x00_rt(rt2x00dev, RT2860) &&
672 !rt2x00_rt(rt2x00dev, RT2872) &&
673 !rt2x00_rt(rt2x00dev, RT3070) &&
692 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
699 if (rt2x00_rt(rt2x00dev, RT3290)) {
700 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
709 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
714 if (rt2800_wait_csr_ready(rt2x00dev))
717 if (rt2x00_is_pci(rt2x00dev)) {
718 if (rt2x00_rt(rt2x00dev, RT3290) ||
719 rt2x00_rt(rt2x00dev, RT3572) ||
720 rt2x00_rt(rt2x00dev, RT5390) ||
721 rt2x00_rt(rt2x00dev, RT5392)) {
722 reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
725 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
727 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
730 rt2800_disable_wpdma(rt2x00dev);
735 rt2800_drv_write_firmware(rt2x00dev, data, len);
741 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
748 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
756 rt2800_disable_wpdma(rt2x00dev);
761 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
762 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
763 if (rt2x00_is_usb(rt2x00dev)) {
764 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
765 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
834 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
844 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
845 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
848 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
851 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
854 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
863 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
864 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
865 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
914 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
987 rt2x00_dbg(entry->queue->rt2x00dev,
999 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1000 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1042 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1073 txdesc.retry = rt2x00dev->long_retry;
1098 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota)
1106 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) {
1112 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
1115 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
1124 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n",
1135 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,
1144 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
1151 rt2x00_dbg(entry->queue->rt2x00dev,
1157 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)
1162 tx_queue_for_each(rt2x00dev, queue) {
1164 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1176 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev)
1180 tx_queue_for_each(rt2x00dev, queue) {
1189 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)
1201 tx_queue_for_each(rt2x00dev, queue) {
1210 rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1231 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev)
1237 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))
1240 queue_for_each(rt2x00dev, queue) {
1256 if (rt2x00dev->intf_sta_count == 0)
1266 rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n");
1269 rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n");
1272 ieee80211_restart_hw(rt2x00dev->hw);
1276 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1282 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1285 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1288 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1290 struct data_queue *queue = rt2x00dev->bcn;
1303 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1308 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1309 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1314 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1317 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1322 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1333 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1336 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1358 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1365 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1368 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1372 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1374 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1381 rt2800_update_beacons_setup(rt2x00dev);
1386 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1396 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1400 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1403 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1411 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1416 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1423 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1426 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1431 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1437 rt2800_update_beacons_setup(rt2x00dev);
1441 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1491 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1495 if (rt2x00_rt(rt2x00dev, RT3290)) {
1496 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1499 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1513 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1515 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1518 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1523 if (rt2x00_is_soc(led->rt2x00dev)) {
1524 reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1541 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1545 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1548 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1559 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1566 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1569 led->rt2x00dev = rt2x00dev;
1579 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1592 rt2800_register_multiwrite(rt2x00dev, offset,
1596 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1600 rt2800_register_write(rt2x00dev, offset, 0);
1603 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1613 reg = rt2800_register_read(rt2x00dev, offset);
1617 rt2800_register_write(rt2x00dev, offset, reg);
1620 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1631 reg = rt2800_register_read(rt2x00dev, offset);
1644 rt2800_register_write(rt2x00dev, offset, reg);
1647 reg = rt2800_register_read(rt2x00dev, offset);
1652 rt2800_register_write(rt2x00dev, offset, reg);
1655 if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
1666 rt2800_register_multiwrite(rt2x00dev, offset,
1670 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1690 rt2800_register_multiwrite(rt2x00dev, offset,
1706 reg = rt2800_register_read(rt2x00dev, offset);
1709 rt2800_register_write(rt2x00dev, offset, reg);
1714 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1715 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1717 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1723 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1747 rt2800_register_multiwrite(rt2x00dev, offset,
1754 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1760 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1764 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1772 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1774 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1780 struct rt2x00_dev *rt2x00dev = hw->priv;
1781 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1793 rt2800_set_max_psdu_len(rt2x00dev);
1821 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1822 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1823 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1824 rt2x00lib_get_bssidx(rt2x00dev, vif));
1832 struct rt2x00_dev *rt2x00dev = hw->priv;
1833 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1839 rt2800_set_max_psdu_len(rt2x00dev);
1848 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1856 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev)
1858 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1859 struct data_queue *queue = rt2x00dev->bcn;
1875 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1886 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1892 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1916 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1920 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1930 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1932 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1938 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1943 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1945 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1950 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1971 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1983 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1989 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
2064 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
2067 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2069 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
2072 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2074 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
2077 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2079 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
2082 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2085 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
2091 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
2094 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2098 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
2101 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2105 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
2107 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2111 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
2114 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2116 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
2118 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2122 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2125 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2129 rt2800_config_ht_opmode(rt2x00dev, erp);
2133 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
2139 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
2140 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
2147 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2149 reg = rt2800_register_read(rt2x00dev, LED_CFG);
2154 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
2159 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2161 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
2167 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
2174 if (rt2x00_is_pci(rt2x00dev)) {
2175 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
2177 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
2178 } else if (rt2x00_is_usb(rt2x00dev))
2179 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
2182 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2185 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2188 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
2194 r1 = rt2800_bbp_read(rt2x00dev, 1);
2195 r3 = rt2800_bbp_read(rt2x00dev, 3);
2197 if (rt2x00_rt(rt2x00dev, RT3572) &&
2198 rt2x00_has_cap_bt_coexist(rt2x00dev))
2199 rt2800_config_3572bt_ant(rt2x00dev);
2209 if (rt2x00_rt(rt2x00dev, RT3572) &&
2210 rt2x00_has_cap_bt_coexist(rt2x00dev))
2225 if (rt2x00_rt(rt2x00dev, RT3070) ||
2226 rt2x00_rt(rt2x00dev, RT3090) ||
2227 rt2x00_rt(rt2x00dev, RT3352) ||
2228 rt2x00_rt(rt2x00dev, RT3390)) {
2229 eeprom = rt2800_eeprom_read(rt2x00dev,
2233 rt2800_set_ant_diversity(rt2x00dev,
2234 rt2x00dev->default_ant.rx);
2239 if (rt2x00_rt(rt2x00dev, RT3572) &&
2240 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2243 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2244 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2254 rt2800_bbp_write(rt2x00dev, 3, r3);
2255 rt2800_bbp_write(rt2x00dev, 1, r1);
2257 if (rt2x00_rt(rt2x00dev, RT3593) ||
2258 rt2x00_rt(rt2x00dev, RT3883)) {
2260 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2262 rt2800_bbp_write(rt2x00dev, 86, 0x46);
2267 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2274 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2277 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2280 if (rt2x00_rt(rt2x00dev, RT3593) ||
2281 rt2x00_rt(rt2x00dev, RT3883)) {
2282 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2286 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2291 if (rt2x00_rt(rt2x00dev, RT3593) ||
2292 rt2x00_rt(rt2x00dev, RT3883)) {
2293 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2297 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2303 rt2x00dev->lna_gain = lna_gain;
2306 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2308 return clk_get_rate(rt2x00dev->clk) == 20000000;
2313 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2318 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2321 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2328 if (rt2x00_is_usb(rt2x00dev)) {
2329 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2342 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2348 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2353 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2355 if (rt2x00dev->default_ant.tx_chain_num == 1)
2358 if (rt2x00dev->default_ant.rx_chain_num == 1) {
2361 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
2393 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2394 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2395 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2396 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2400 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2401 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2402 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2403 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2407 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2408 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2409 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2410 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2413 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2418 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2421 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2423 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2425 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2427 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2429 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2431 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2433 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2435 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2437 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2439 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2442 rt2x00dev->default_ant.rx_chain_num <= 1);
2444 rt2x00dev->default_ant.rx_chain_num <= 2);
2447 rt2x00dev->default_ant.tx_chain_num <= 1);
2449 rt2x00dev->default_ant.tx_chain_num <= 2);
2450 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2452 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2453 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2454 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2456 if (rt2x00_rt(rt2x00dev, RT3390)) {
2469 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2471 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2473 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2475 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2477 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2479 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2481 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2483 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2488 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2491 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2496 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2501 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2502 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2504 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2505 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2508 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2509 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2511 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2517 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2519 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2524 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2526 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2537 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2539 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2550 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2552 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2559 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2567 switch (rt2x00dev->default_ant.tx_chain_num) {
2576 switch (rt2x00dev->default_ant.rx_chain_num) {
2585 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2587 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2588 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2589 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2592 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2593 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2595 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2596 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2600 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2601 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2602 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2603 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2604 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2608 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2609 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2610 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2611 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2612 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2613 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2614 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2615 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2617 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2622 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2623 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2624 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2625 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2626 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2630 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2631 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2633 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2634 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2635 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2637 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2638 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2639 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2641 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2642 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2643 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2645 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2646 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2647 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2650 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2656 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2658 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2660 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2663 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2668 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2676 bbp = rt2800_bbp_read(rt2x00dev, 109);
2679 rt2800_bbp_write(rt2x00dev, 109, bbp);
2681 bbp = rt2800_bbp_read(rt2x00dev, 110);
2683 rt2800_bbp_write(rt2x00dev, 110, bbp);
2687 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2688 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2693 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2695 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2698 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2699 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2701 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2703 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2705 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2711 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2713 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2719 if (rt2x00_is_usb(rt2x00dev))
2726 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2728 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2734 if (rt2x00_is_usb(rt2x00dev))
2741 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2743 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2749 if (rt2x00_is_usb(rt2x00dev))
2756 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2758 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2768 switch (rt2x00dev->default_ant.tx_chain_num) {
2780 switch (rt2x00dev->default_ant.rx_chain_num) {
2791 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2793 rt2800_freq_cal_mode1(rt2x00dev);
2810 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2817 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2819 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2822 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2825 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2830 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2832 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2837 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2839 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2844 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2846 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2855 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2857 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2859 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2861 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2864 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2865 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2867 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2868 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2871 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2873 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2875 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2883 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2885 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2894 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2896 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2898 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2900 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
2905 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2908 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2909 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2911 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2912 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2916 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2927 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2933 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2935 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2940 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2942 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2947 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2949 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2954 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2956 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2960 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
2974 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2976 rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
2978 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2980 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2981 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2984 rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
2986 rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
2989 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
2991 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2993 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2995 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3005 switch (rt2x00dev->default_ant.tx_chain_num) {
3017 switch (rt2x00dev->default_ant.rx_chain_num) {
3028 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3030 rt2800_freq_cal_mode1(rt2x00dev);
3032 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3037 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3040 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
3042 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3045 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3047 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
3050 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
3052 rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
3055 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
3060 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
3074 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3077 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
3079 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
3089 rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
3099 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3101 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
3103 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3105 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
3107 rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
3109 rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
3111 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
3113 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
3128 rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
3129 rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
3130 rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
3132 rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
3137 rt2800_bbp_write(rt2x00dev, 109, bbp);
3139 bbp = rt2800_bbp_read(rt2x00dev, 110);
3142 rt2800_bbp_write(rt2x00dev, 110, bbp);
3144 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3146 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
3148 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
3151 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3153 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3157 bbp = rt2800_bbp_read(rt2x00dev, 49);
3159 rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
3160 rt2800_bbp_write(rt2x00dev, 49, bbp);
3168 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
3175 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3176 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3177 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3179 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3181 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3186 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3188 rt2800_freq_cal_mode1(rt2x00dev);
3192 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
3194 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3197 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
3199 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
3201 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
3205 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
3212 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3213 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3215 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
3216 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
3217 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
3220 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
3222 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
3225 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
3227 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
3229 rt2800_freq_cal_mode1(rt2x00dev);
3231 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3235 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
3240 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
3248 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3250 rt2800_rfcsr_write(rt2x00dev, 31, 80);
3253 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
3261 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3262 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3263 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3265 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3267 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3272 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3274 if (rt2x00_rt(rt2x00dev, RT5392)) {
3275 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3281 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3284 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3285 if (rt2x00_rt(rt2x00dev, RT5392)) {
3293 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3295 rt2800_freq_cal_mode1(rt2x00dev);
3297 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3298 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3307 rt2800_rfcsr_write(rt2x00dev, 55,
3309 rt2800_rfcsr_write(rt2x00dev, 59,
3316 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
3319 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3327 rt2800_rfcsr_write(rt2x00dev, 55,
3329 rt2800_rfcsr_write(rt2x00dev, 59,
3331 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3332 rt2x00_rt(rt2x00dev, RT5392) ||
3333 rt2x00_rt(rt2x00dev, RT6352)) {
3338 rt2800_rfcsr_write(rt2x00dev, 59,
3340 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
3345 rt2800_rfcsr_write(rt2x00dev, 59,
3351 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
3364 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
3367 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3370 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
3372 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9);
3376 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
3378 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3381 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3384 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
3386 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
3387 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3388 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3389 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3390 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
3391 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3392 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3393 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
3394 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3395 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3396 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
3397 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
3398 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
3399 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
3400 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
3401 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
3402 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
3403 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
3404 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3405 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
3406 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3407 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3408 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
3409 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3410 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3411 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3412 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3413 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3418 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
3419 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
3423 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
3424 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
3426 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
3428 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
3432 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
3434 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3440 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
3442 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3443 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3444 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3445 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3446 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3447 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3448 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3449 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3450 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3451 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3452 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3453 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3454 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3455 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3461 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3462 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3463 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3464 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3466 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3468 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3469 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3470 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3471 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3472 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3473 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3474 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3475 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3477 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3478 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3480 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3481 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3484 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3485 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3486 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3490 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3491 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3492 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3494 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3495 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3497 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3498 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3501 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3502 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3503 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3504 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3506 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3507 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3508 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3509 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3512 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3514 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3516 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3518 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3519 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3521 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3523 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3525 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3527 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3529 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3531 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3533 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3535 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3537 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3539 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3546 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3553 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3555 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3562 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3564 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3569 rt2x00dev->default_ant.tx_chain_num >= 1);
3571 rt2x00dev->default_ant.tx_chain_num == 2);
3575 rt2x00dev->default_ant.rx_chain_num >= 1);
3577 rt2x00dev->default_ant.rx_chain_num == 2);
3580 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3581 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3584 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3586 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3589 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3590 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3594 rt2800_freq_cal_mode1(rt2x00dev);
3597 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3599 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3602 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3603 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3604 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3606 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3607 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3608 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3609 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3612 rt2800_bbp_write(rt2x00dev, 195, 128);
3613 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3614 rt2800_bbp_write(rt2x00dev, 195, 129);
3615 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3616 rt2800_bbp_write(rt2x00dev, 195, 130);
3617 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3618 rt2800_bbp_write(rt2x00dev, 195, 131);
3619 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3620 rt2800_bbp_write(rt2x00dev, 195, 133);
3621 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3622 rt2800_bbp_write(rt2x00dev, 195, 124);
3623 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3626 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3631 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3639 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3641 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3642 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3648 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3650 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3652 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3654 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3659 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3661 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3666 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3668 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3675 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3677 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3679 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3681 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3683 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3685 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3688 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3690 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3692 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3694 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3696 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3698 rt2x00dev->default_ant.tx_chain_num != 1);
3699 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3701 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3703 rt2x00dev->default_ant.tx_chain_num != 1);
3705 rt2x00dev->default_ant.rx_chain_num != 1);
3706 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3708 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3710 rt2x00dev->default_ant.tx_chain_num != 1);
3711 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3715 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3716 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3717 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3718 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3719 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3721 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3722 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3723 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3724 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3725 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3729 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3730 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3732 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3733 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3736 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3739 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3741 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3749 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3752 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3753 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3756 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3757 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3760 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3761 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3764 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3766 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3769 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3770 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3773 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3774 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3777 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3778 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3781 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3785 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3803 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3809 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3812 target_power = rt2800_eeprom_read(rt2x00dev,
3817 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3819 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3821 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3824 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3826 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3829 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
3837 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
3840 bbp = rt2800_bbp_read(rt2x00dev, 30);
3842 rt2800_bbp_write(rt2x00dev, 30, bbp);
3843 rt2800_rfcsr_write(rt2x00dev, 39, 0);
3844 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3845 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3847 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3849 bbp = rt2800_bbp_read(rt2x00dev, 30);
3851 rt2800_bbp_write(rt2x00dev, 30, bbp);
3852 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3853 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3854 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3856 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3858 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
3860 rt2800_vco_calibration(rt2x00dev);
3863 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3869 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3870 reg = rt2800_bbp_read(rt2x00dev, 27);
3872 rt2800_bbp_write(rt2x00dev, 27, reg);
3874 rt2800_bbp_write(rt2x00dev, word, value);
3878 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3883 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3885 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3887 cal = rt2x00_eeprom_byte(rt2x00dev,
3890 cal = rt2x00_eeprom_byte(rt2x00dev,
3893 cal = rt2x00_eeprom_byte(rt2x00dev,
3897 rt2800_bbp_write(rt2x00dev, 159, cal);
3900 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3902 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3904 cal = rt2x00_eeprom_byte(rt2x00dev,
3907 cal = rt2x00_eeprom_byte(rt2x00dev,
3910 cal = rt2x00_eeprom_byte(rt2x00dev,
3914 rt2800_bbp_write(rt2x00dev, 159, cal);
3917 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3919 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3921 cal = rt2x00_eeprom_byte(rt2x00dev,
3924 cal = rt2x00_eeprom_byte(rt2x00dev,
3927 cal = rt2x00_eeprom_byte(rt2x00dev,
3931 rt2800_bbp_write(rt2x00dev, 159, cal);
3934 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3936 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3938 cal = rt2x00_eeprom_byte(rt2x00dev,
3941 cal = rt2x00_eeprom_byte(rt2x00dev,
3944 cal = rt2x00_eeprom_byte(rt2x00dev,
3948 rt2800_bbp_write(rt2x00dev, 159, cal);
3953 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3954 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3955 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3958 rt2800_bbp_write(rt2x00dev, 158, 0x03);
3959 cal = rt2x00_eeprom_byte(rt2x00dev,
3961 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3964 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3968 if (rt2x00_rt(rt2x00dev, RT3593) ||
3969 rt2x00_rt(rt2x00dev, RT3883))
3975 if (rt2x00_rt(rt2x00dev, RT3593) ||
3976 rt2x00_rt(rt2x00dev, RT3883))
3983 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
3989 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
3991 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3994 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3997 rt2800_bbp_write(rt2x00dev, 70, 0x00);
4000 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4003 rt2800_bbp_write(rt2x00dev, 62, 0x1d);
4004 rt2800_bbp_write(rt2x00dev, 63, 0x1d);
4005 rt2800_bbp_write(rt2x00dev, 64, 0x1d);
4007 rt2800_bbp_write(rt2x00dev, 62, 0x2d);
4008 rt2800_bbp_write(rt2x00dev, 63, 0x2d);
4009 rt2800_bbp_write(rt2x00dev, 64, 0x2d);
4013 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
4022 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4024 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4026 if (rt2x00dev->default_ant.tx_chain_num > 2)
4028 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4031 switch (rt2x00dev->chip.rt) {
4033 rt3883_bbp_adjust(rt2x00dev, rf);
4037 switch (rt2x00dev->chip.rf) {
4043 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
4046 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
4049 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
4052 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
4055 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
4058 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
4068 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
4071 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
4074 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
4077 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
4080 if (rt2x00_rf(rt2x00dev, RF3070) ||
4081 rt2x00_rf(rt2x00dev, RF3290) ||
4082 rt2x00_rf(rt2x00dev, RF3322) ||
4083 rt2x00_rf(rt2x00dev, RF5350) ||
4084 rt2x00_rf(rt2x00dev, RF5360) ||
4085 rt2x00_rf(rt2x00dev, RF5362) ||
4086 rt2x00_rf(rt2x00dev, RF5370) ||
4087 rt2x00_rf(rt2x00dev, RF5372) ||
4088 rt2x00_rf(rt2x00dev, RF5390) ||
4089 rt2x00_rf(rt2x00dev, RF5392)) {
4090 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
4091 if (rt2x00_rf(rt2x00dev, RF3322)) {
4102 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4104 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4106 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4113 if (rt2x00_rt(rt2x00dev, RT3352)) {
4114 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4115 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4116 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4118 rt2800_bbp_write(rt2x00dev, 27, 0x0);
4119 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4120 rt2800_bbp_write(rt2x00dev, 27, 0x20);
4121 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4122 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4123 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4124 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4127 rt2800_bbp_write(rt2x00dev, 70, 0x00);
4129 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4133 rt2800_bbp_write(rt2x00dev, 105, 0x04);
4135 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4137 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4138 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4139 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4140 rt2800_bbp_write(rt2x00dev, 77, 0x98);
4141 } else if (rt2x00_rt(rt2x00dev, RT3883)) {
4142 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4143 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4144 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4146 if (rt2x00dev->default_ant.rx_chain_num > 1)
4147 rt2800_bbp_write(rt2x00dev, 86, 0x46);
4149 rt2800_bbp_write(rt2x00dev, 86, 0);
4151 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4152 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4153 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4154 if (rt2x00_rt(rt2x00dev, RT6352))
4155 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4157 rt2800_bbp_write(rt2x00dev, 86, 0);
4161 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4162 !rt2x00_rt(rt2x00dev, RT5392) &&
4163 !rt2x00_rt(rt2x00dev, RT6352)) {
4164 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4165 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4166 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4167 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4169 if (rt2x00_rt(rt2x00dev, RT3593))
4170 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4172 rt2800_bbp_write(rt2x00dev, 82, 0x84);
4173 rt2800_bbp_write(rt2x00dev, 75, 0x50);
4175 if (rt2x00_rt(rt2x00dev, RT3593) ||
4176 rt2x00_rt(rt2x00dev, RT3883))
4177 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
4181 if (rt2x00_rt(rt2x00dev, RT3572))
4182 rt2800_bbp_write(rt2x00dev, 82, 0x94);
4183 else if (rt2x00_rt(rt2x00dev, RT3593) ||
4184 rt2x00_rt(rt2x00dev, RT3883))
4185 rt2800_bbp_write(rt2x00dev, 82, 0x82);
4186 else if (!rt2x00_rt(rt2x00dev, RT6352))
4187 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
4189 if (rt2x00_rt(rt2x00dev, RT3593) ||
4190 rt2x00_rt(rt2x00dev, RT3883))
4191 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
4193 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
4194 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4196 rt2800_bbp_write(rt2x00dev, 75, 0x50);
4199 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
4203 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
4205 if (rt2x00_rt(rt2x00dev, RT3572))
4206 rt2800_rfcsr_write(rt2x00dev, 8, 0);
4208 if (rt2x00_rt(rt2x00dev, RT6352)) {
4209 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4215 switch (rt2x00dev->default_ant.tx_chain_num) {
4234 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
4242 switch (rt2x00dev->default_ant.rx_chain_num) {
4263 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4265 if (rt2x00_rt(rt2x00dev, RT3572)) {
4266 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
4270 reg = 0x1c + (2 * rt2x00dev->lna_gain);
4272 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4274 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4277 if (rt2x00_rt(rt2x00dev, RT3593)) {
4278 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
4281 if (rt2x00_is_usb(rt2x00dev) ||
4282 rt2x00_is_pcie(rt2x00dev)) {
4292 if (rt2x00_is_usb(rt2x00dev)) {
4301 } else if (rt2x00_is_pcie(rt2x00dev)) {
4307 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4311 reg = 0x1c + 2 * rt2x00dev->lna_gain;
4313 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4315 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4320 if (rt2x00_rt(rt2x00dev, RT3883)) {
4322 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4324 rt2800_bbp_write(rt2x00dev, 105, 0x04);
4328 reg = 0x2e + rt2x00dev->lna_gain;
4330 reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
4332 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4337 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
4340 if (rt2x00_rt(rt2x00dev, RT6352) &&
4341 rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4347 rt2800_bbp_write(rt2x00dev, 195, 141);
4348 rt2800_bbp_write(rt2x00dev, 196, reg);
4355 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
4356 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4358 if (rt2x00_rt(rt2x00dev, RT5592))
4359 rt2800_iq_calibrate(rt2x00dev, rf->channel);
4362 bbp = rt2800_bbp_read(rt2x00dev, 4);
4364 rt2800_bbp_write(rt2x00dev, 4, bbp);
4366 bbp = rt2800_bbp_read(rt2x00dev, 3);
4368 rt2800_bbp_write(rt2x00dev, 3, bbp);
4370 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4372 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
4373 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4374 rt2800_bbp_write(rt2x00dev, 73, 0x16);
4376 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4377 rt2800_bbp_write(rt2x00dev, 70, 0x08);
4378 rt2800_bbp_write(rt2x00dev, 73, 0x11);
4387 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
4388 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
4389 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
4394 if (rt2x00_rt(rt2x00dev, RT3352) ||
4395 rt2x00_rt(rt2x00dev, RT5350)) {
4396 bbp = rt2800_bbp_read(rt2x00dev, 49);
4398 rt2800_bbp_write(rt2x00dev, 49, bbp);
4402 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
4413 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
4425 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
4426 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
4432 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
4438 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
4444 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
4450 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
4457 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
4463 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
4469 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
4475 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
4481 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
4498 current_tssi = rt2800_bbp_read(rt2x00dev, 49);
4519 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4527 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4533 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4563 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4568 if (rt2x00_has_cap_power_limit(rt2x00dev))
4584 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4594 if (rt2x00_rt(rt2x00dev, RT3593))
4597 if (rt2x00_rt(rt2x00dev, RT3883))
4600 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4608 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4614 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4655 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4672 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4679 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4683 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4688 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4699 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4710 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4721 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4731 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4736 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4747 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4758 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4768 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4773 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4784 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4795 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4806 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4816 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4821 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4832 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4843 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4854 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4864 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4869 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4880 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4891 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4902 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4912 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4917 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4928 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4939 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4949 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4954 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4965 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4976 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4985 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4993 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4998 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5007 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
5008 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
5009 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
5010 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
5011 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
5012 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
5013 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
5014 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
5015 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
5016 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
5018 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
5020 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
5022 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
5024 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
5026 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
5030 rt2x00_dbg(rt2x00dev,
5033 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
5041 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
5053 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5056 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
5074 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5092 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5109 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
5112 rt2800_register_write(rt2x00dev,
5118 rt2800_register_write(rt2x00dev,
5136 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
5141 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
5144 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
5148 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
5151 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
5155 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
5158 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
5160 rt2800_config_alc(rt2x00dev, chan, power_level);
5174 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
5188 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5197 switch (rt2x00dev->chip.rt) {
5205 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
5217 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
5237 r1 = rt2800_bbp_read(rt2x00dev, 1);
5239 rt2800_bbp_write(rt2x00dev, 1, r1);
5248 reg = rt2800_register_read(rt2x00dev, offset);
5251 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5263 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5274 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5285 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5296 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5301 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5313 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5324 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5335 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5346 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5350 rt2800_register_write(rt2x00dev, offset, reg);
5357 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5361 if (rt2x00_rt(rt2x00dev, RT3593) ||
5362 rt2x00_rt(rt2x00dev, RT3883))
5363 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
5364 else if (rt2x00_rt(rt2x00dev, RT6352))
5365 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
5367 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
5370 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
5372 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
5373 rt2x00dev->tx_power);
5377 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
5391 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5393 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5395 switch (rt2x00dev->chip.rf) {
5402 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
5404 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
5418 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
5420 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5424 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
5425 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
5426 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
5428 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
5433 rt2x00dev->chip.rf);
5440 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5441 if (rt2x00dev->rf_channel <= 14) {
5442 switch (rt2x00dev->default_ant.tx_chain_num) {
5455 switch (rt2x00dev->default_ant.tx_chain_num) {
5468 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5470 if (rt2x00_rt(rt2x00dev, RT6352)) {
5471 if (rt2x00dev->default_ant.rx_chain_num == 1) {
5472 rt2800_bbp_write(rt2x00dev, 91, 0x07);
5473 rt2800_bbp_write(rt2x00dev, 95, 0x1A);
5474 rt2800_bbp_write(rt2x00dev, 195, 128);
5475 rt2800_bbp_write(rt2x00dev, 196, 0xA0);
5476 rt2800_bbp_write(rt2x00dev, 195, 170);
5477 rt2800_bbp_write(rt2x00dev, 196, 0x12);
5478 rt2800_bbp_write(rt2x00dev, 195, 171);
5479 rt2800_bbp_write(rt2x00dev, 196, 0x10);
5481 rt2800_bbp_write(rt2x00dev, 91, 0x06);
5482 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
5483 rt2800_bbp_write(rt2x00dev, 195, 128);
5484 rt2800_bbp_write(rt2x00dev, 196, 0xE0);
5485 rt2800_bbp_write(rt2x00dev, 195, 170);
5486 rt2800_bbp_write(rt2x00dev, 196, 0x30);
5487 rt2800_bbp_write(rt2x00dev, 195, 171);
5488 rt2800_bbp_write(rt2x00dev, 196, 0x30);
5491 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
5492 rt2800_bbp_write(rt2x00dev, 75, 0x68);
5493 rt2800_bbp_write(rt2x00dev, 76, 0x4C);
5494 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
5495 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
5496 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
5509 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5514 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5519 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5522 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5531 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5533 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5538 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5540 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5542 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5546 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5548 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5552 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5557 rt2800_config_lna_gain(rt2x00dev, libconf);
5560 rt2800_config_channel(rt2x00dev, libconf->conf,
5562 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5566 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5569 rt2800_config_retry_limit(rt2x00dev, libconf);
5571 rt2800_config_ps(rt2x00dev, libconf);
5578 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5585 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5590 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5594 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5595 if (rt2x00_rt(rt2x00dev, RT3070) ||
5596 rt2x00_rt(rt2x00dev, RT3071) ||
5597 rt2x00_rt(rt2x00dev, RT3090) ||
5598 rt2x00_rt(rt2x00dev, RT3290) ||
5599 rt2x00_rt(rt2x00dev, RT3390) ||
5600 rt2x00_rt(rt2x00dev, RT3572) ||
5601 rt2x00_rt(rt2x00dev, RT3593) ||
5602 rt2x00_rt(rt2x00dev, RT5390) ||
5603 rt2x00_rt(rt2x00dev, RT5392) ||
5604 rt2x00_rt(rt2x00dev, RT5592) ||
5605 rt2x00_rt(rt2x00dev, RT6352))
5606 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5608 vgc = 0x2e + rt2x00dev->lna_gain;
5610 if (rt2x00_rt(rt2x00dev, RT3593) ||
5611 rt2x00_rt(rt2x00dev, RT3883))
5612 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5613 else if (rt2x00_rt(rt2x00dev, RT5592))
5614 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5616 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5617 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5619 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5626 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5630 if (rt2x00_rt(rt2x00dev, RT3572) ||
5631 rt2x00_rt(rt2x00dev, RT3593) ||
5632 rt2x00_rt(rt2x00dev, RT3883) ||
5633 rt2x00_rt(rt2x00dev, RT6352)) {
5634 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5636 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5637 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5638 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5640 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5648 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5650 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5654 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5659 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5667 vgc = rt2800_get_default_vgc(rt2x00dev);
5669 switch (rt2x00dev->chip.rt) {
5673 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5696 rt2800_set_vgc(rt2x00dev, qual, vgc);
5703 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5705 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5711 rt2800_disable_wpdma(rt2x00dev);
5713 ret = rt2800_drv_init_registers(rt2x00dev);
5717 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5718 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5720 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5722 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5729 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5731 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5733 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5736 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5738 if (rt2x00_rt(rt2x00dev, RT3290)) {
5739 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5742 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5745 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5749 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5752 reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5756 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5758 reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5760 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5762 reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5767 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5769 reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5771 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5774 if (rt2x00_rt(rt2x00dev, RT3071) ||
5775 rt2x00_rt(rt2x00dev, RT3090) ||
5776 rt2x00_rt(rt2x00dev, RT3290) ||
5777 rt2x00_rt(rt2x00dev, RT3390)) {
5779 if (rt2x00_rt(rt2x00dev, RT3290))
5780 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5783 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5786 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5787 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5788 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5789 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5790 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5792 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5795 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5798 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5800 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
5801 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5803 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5804 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5805 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5807 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5808 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5810 } else if (rt2800_is_305x_soc(rt2x00dev)) {
5811 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5812 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5813 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5814 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
5815 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5816 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5817 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5818 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
5819 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5820 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5821 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
5822 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5823 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5824 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5825 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5828 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5831 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5834 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5837 } else if (rt2x00_rt(rt2x00dev, RT3883)) {
5838 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5839 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5840 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
5841 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
5842 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
5843 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
5844 rt2x00_rt(rt2x00dev, RT5392)) {
5845 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5846 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5847 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5848 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5849 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5850 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5851 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5852 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
5853 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5854 } else if (rt2x00_rt(rt2x00dev, RT6352)) {
5855 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5856 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
5857 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5858 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
5859 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5860 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5861 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5862 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5863 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5865 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5867 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
5869 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
5871 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5872 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5875 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
5884 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
5886 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
5890 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5892 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
5894 if (rt2x00_is_usb(rt2x00dev)) {
5896 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
5897 rt2x00_rt(rt2x00dev, RT2883) ||
5898 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
5906 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5908 reg = rt2800_register_read(rt2x00dev, LED_CFG);
5916 rt2800_register_write(rt2x00dev, LED_CFG, reg);
5918 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5920 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5927 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5929 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
5937 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5939 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
5950 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5952 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
5963 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5965 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
5976 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5978 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
5989 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5991 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
6002 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6004 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
6015 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6017 if (rt2x00_is_usb(rt2x00dev)) {
6018 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
6020 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
6030 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6037 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
6048 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
6050 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
6051 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
6053 if (rt2x00_rt(rt2x00dev, RT3883)) {
6054 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
6055 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
6058 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
6063 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6065 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
6074 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
6080 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
6082 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
6088 rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0);
6091 rt2800_config_wcid(rt2x00dev, NULL, i);
6092 rt2800_delete_wcid_attr(rt2x00dev, i);
6100 if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
6102 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
6108 rt2800_clear_beacon_register(rt2x00dev, i);
6110 if (rt2x00_is_usb(rt2x00dev)) {
6111 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6113 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6114 } else if (rt2x00_is_pcie(rt2x00dev)) {
6115 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6117 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6118 } else if (rt2x00_is_soc(rt2x00dev)) {
6136 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6138 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6141 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
6150 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
6152 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
6161 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
6163 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
6172 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
6174 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
6179 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
6184 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
6187 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
6194 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
6195 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
6196 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
6197 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
6198 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
6199 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
6204 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
6206 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
6211 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
6217 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
6222 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
6228 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
6235 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
6239 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
6248 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6249 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6253 value = rt2800_bbp_read(rt2x00dev, 0);
6259 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
6263 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
6267 value = rt2800_bbp_read(rt2x00dev, 4);
6269 rt2800_bbp_write(rt2x00dev, 4, value);
6272 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
6274 rt2800_bbp_write(rt2x00dev, 142, 1);
6275 rt2800_bbp_write(rt2x00dev, 143, 57);
6278 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
6294 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
6295 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
6299 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
6301 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6302 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6303 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
6304 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6305 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6306 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6307 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6308 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6309 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
6310 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6311 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6312 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6313 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6314 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6315 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6316 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6319 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
6324 value = rt2800_bbp_read(rt2x00dev, 138);
6325 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6330 rt2800_bbp_write(rt2x00dev, 138, value);
6333 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
6335 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6337 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6338 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6340 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6341 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6343 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6345 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6346 rt2800_bbp_write(rt2x00dev, 80, 0x08);
6348 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6350 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6352 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6354 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6356 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6358 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6360 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6362 rt2800_bbp_write(rt2x00dev, 105, 0x01);
6364 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6367 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
6369 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6370 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6372 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
6373 rt2800_bbp_write(rt2x00dev, 69, 0x16);
6374 rt2800_bbp_write(rt2x00dev, 73, 0x12);
6376 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6377 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6380 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6382 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6384 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6386 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6388 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
6389 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6391 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6393 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6395 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6397 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6399 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6401 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6403 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6406 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
6408 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6409 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6411 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6412 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6414 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6416 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6417 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6418 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6420 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6422 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6424 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6426 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6428 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6430 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6432 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
6433 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
6434 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
6435 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6437 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6439 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6441 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6443 if (rt2x00_rt(rt2x00dev, RT3071) ||
6444 rt2x00_rt(rt2x00dev, RT3090))
6445 rt2800_disable_unused_dac_adc(rt2x00dev);
6448 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
6452 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6454 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6456 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6457 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6459 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6461 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6462 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6463 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6464 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6466 rt2800_bbp_write(rt2x00dev, 77, 0x58);
6468 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6470 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
6471 rt2800_bbp_write(rt2x00dev, 79, 0x18);
6472 rt2800_bbp_write(rt2x00dev, 80, 0x09);
6473 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6475 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6477 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6479 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6481 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6483 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6485 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6487 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6489 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6491 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
6493 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6495 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6497 rt2800_bbp_write(rt2x00dev, 67, 0x24);
6498 rt2800_bbp_write(rt2x00dev, 143, 0x04);
6499 rt2800_bbp_write(rt2x00dev, 142, 0x99);
6500 rt2800_bbp_write(rt2x00dev, 150, 0x30);
6501 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
6502 rt2800_bbp_write(rt2x00dev, 152, 0x20);
6503 rt2800_bbp_write(rt2x00dev, 153, 0x34);
6504 rt2800_bbp_write(rt2x00dev, 154, 0x40);
6505 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
6506 rt2800_bbp_write(rt2x00dev, 253, 0x04);
6508 value = rt2800_bbp_read(rt2x00dev, 47);
6510 rt2800_bbp_write(rt2x00dev, 47, value);
6513 value = rt2800_bbp_read(rt2x00dev, 3);
6516 rt2800_bbp_write(rt2x00dev, 3, value);
6519 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
6521 rt2800_bbp_write(rt2x00dev, 3, 0x00);
6522 rt2800_bbp_write(rt2x00dev, 4, 0x50);
6524 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6526 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6528 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6529 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6531 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6533 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6534 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6535 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6536 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6538 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6540 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6542 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6543 rt2800_bbp_write(rt2x00dev, 80, 0x08);
6544 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6546 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6548 if (rt2x00_rt(rt2x00dev, RT5350)) {
6549 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6550 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6552 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6553 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6556 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6558 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6560 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6562 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6564 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6566 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6568 if (rt2x00_rt(rt2x00dev, RT5350)) {
6569 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6570 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6572 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6573 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6576 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6578 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6580 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6582 rt2800_bbp_write(rt2x00dev, 179, 0x02);
6583 rt2800_bbp_write(rt2x00dev, 180, 0x00);
6584 rt2800_bbp_write(rt2x00dev, 182, 0x40);
6585 rt2800_bbp_write(rt2x00dev, 180, 0x01);
6586 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6587 rt2800_bbp_write(rt2x00dev, 179, 0x00);
6589 rt2800_bbp_write(rt2x00dev, 142, 0x04);
6590 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6591 rt2800_bbp_write(rt2x00dev, 142, 0x06);
6592 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6593 rt2800_bbp_write(rt2x00dev, 142, 0x07);
6594 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6595 rt2800_bbp_write(rt2x00dev, 142, 0x08);
6596 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6598 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6600 if (rt2x00_rt(rt2x00dev, RT5350)) {
6602 rt2800_bbp_write(rt2x00dev, 150, 0x40);
6604 rt2800_bbp_write(rt2x00dev, 151, 0x30);
6605 rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6607 rt2800_bbp_write(rt2x00dev, 154, 0);
6611 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6613 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6614 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6616 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6617 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6619 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6621 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6622 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6623 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6625 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6627 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6629 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6631 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6633 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6635 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6637 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6638 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6640 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6642 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6644 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6646 rt2800_disable_unused_dac_adc(rt2x00dev);
6649 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6651 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6653 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6654 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6656 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6657 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6659 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6661 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6662 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6663 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6665 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6667 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6669 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6671 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6673 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6675 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6677 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6679 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6681 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6683 rt2800_disable_unused_dac_adc(rt2x00dev);
6686 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6688 rt2800_init_bbp_early(rt2x00dev);
6690 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6691 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6692 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6693 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6695 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6698 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6699 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6702 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev)
6704 rt2800_init_bbp_early(rt2x00dev);
6706 rt2800_bbp_write(rt2x00dev, 4, 0x50);
6707 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6709 rt2800_bbp_write(rt2x00dev, 86, 0x46);
6710 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6712 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6714 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6715 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6716 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6717 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6718 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6719 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6720 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6723 rt2800_bbp_write(rt2x00dev, 179, 0x02);
6724 rt2800_bbp_write(rt2x00dev, 180, 0x00);
6725 rt2800_bbp_write(rt2x00dev, 182, 0x40);
6726 rt2800_bbp_write(rt2x00dev, 180, 0x01);
6727 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6729 rt2800_bbp_write(rt2x00dev, 179, 0x00);
6732 rt2800_bbp_write(rt2x00dev, 142, 0x04);
6733 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6734 rt2800_bbp_write(rt2x00dev, 142, 0x06);
6735 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6736 rt2800_bbp_write(rt2x00dev, 142, 0x07);
6737 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6738 rt2800_bbp_write(rt2x00dev, 142, 0x08);
6739 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6740 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6743 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6749 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6751 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6753 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6754 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6756 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6758 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6759 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6760 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6761 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6763 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6765 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6767 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6768 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6769 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6771 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6773 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6775 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6777 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6779 if (rt2x00_rt(rt2x00dev, RT5392))
6780 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6782 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6784 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6786 if (rt2x00_rt(rt2x00dev, RT5392)) {
6787 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6788 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6791 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6793 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6795 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6797 if (rt2x00_rt(rt2x00dev, RT5390))
6798 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6799 else if (rt2x00_rt(rt2x00dev, RT5392))
6800 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6804 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6806 if (rt2x00_rt(rt2x00dev, RT5392)) {
6807 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6808 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6811 rt2800_disable_unused_dac_adc(rt2x00dev);
6813 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6819 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6822 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6831 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6835 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
6836 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
6837 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6838 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6839 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6842 value = rt2800_bbp_read(rt2x00dev, 152);
6847 rt2800_bbp_write(rt2x00dev, 152, value);
6849 rt2800_init_freq_calibration(rt2x00dev);
6852 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6858 rt2800_init_bbp_early(rt2x00dev);
6860 value = rt2800_bbp_read(rt2x00dev, 105);
6862 rt2x00dev->default_ant.rx_chain_num == 2);
6863 rt2800_bbp_write(rt2x00dev, 105, value);
6865 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6867 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6868 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6869 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6870 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6871 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6872 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6873 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6874 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6875 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6876 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6877 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6878 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6879 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6880 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6881 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6882 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6883 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6884 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6885 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6886 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6888 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6889 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6890 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6891 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6892 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6893 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6896 rt2800_init_bbp_5592_glrt(rt2x00dev);
6898 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6900 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6903 value = rt2800_bbp_read(rt2x00dev, 152);
6911 rt2800_bbp_write(rt2x00dev, 152, value);
6913 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6914 value = rt2800_bbp_read(rt2x00dev, 254);
6916 rt2800_bbp_write(rt2x00dev, 254, value);
6919 rt2800_init_freq_calibration(rt2x00dev);
6921 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6922 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6923 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6926 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
6929 rt2800_bbp_write(rt2x00dev, 195, reg);
6930 rt2800_bbp_write(rt2x00dev, 196, value);
6933 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
6936 rt2800_bbp_write(rt2x00dev, 158, reg);
6937 rt2800_bbp_write(rt2x00dev, 159, value);
6940 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
6942 rt2800_bbp_write(rt2x00dev, 158, reg);
6943 return rt2800_bbp_read(rt2x00dev, 159);
6946 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
6951 bbp = rt2800_bbp_read(rt2x00dev, 105);
6953 rt2x00dev->default_ant.rx_chain_num == 2);
6954 rt2800_bbp_write(rt2x00dev, 105, bbp);
6957 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6960 bbp = rt2800_bbp_read(rt2x00dev, 1);
6962 rt2800_bbp_write(rt2x00dev, 1, bbp);
6965 rt2800_bbp_write(rt2x00dev, 3, 0x08);
6966 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
6967 rt2800_bbp_write(rt2x00dev, 6, 0x08);
6968 rt2800_bbp_write(rt2x00dev, 14, 0x09);
6969 rt2800_bbp_write(rt2x00dev, 15, 0xFF);
6970 rt2800_bbp_write(rt2x00dev, 16, 0x01);
6971 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6972 rt2800_bbp_write(rt2x00dev, 21, 0x00);
6973 rt2800_bbp_write(rt2x00dev, 22, 0x00);
6974 rt2800_bbp_write(rt2x00dev, 27, 0x00);
6975 rt2800_bbp_write(rt2x00dev, 28, 0x00);
6976 rt2800_bbp_write(rt2x00dev, 30, 0x00);
6977 rt2800_bbp_write(rt2x00dev, 31, 0x48);
6978 rt2800_bbp_write(rt2x00dev, 47, 0x40);
6979 rt2800_bbp_write(rt2x00dev, 62, 0x00);
6980 rt2800_bbp_write(rt2x00dev, 63, 0x00);
6981 rt2800_bbp_write(rt2x00dev, 64, 0x00);
6982 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6983 rt2800_bbp_write(rt2x00dev, 66, 0x1C);
6984 rt2800_bbp_write(rt2x00dev, 67, 0x20);
6985 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6986 rt2800_bbp_write(rt2x00dev, 69, 0x10);
6987 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6988 rt2800_bbp_write(rt2x00dev, 73, 0x18);
6989 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6990 rt2800_bbp_write(rt2x00dev, 75, 0x60);
6991 rt2800_bbp_write(rt2x00dev, 76, 0x44);
6992 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6993 rt2800_bbp_write(rt2x00dev, 78, 0x1E);
6994 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
6995 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
6996 rt2800_bbp_write(rt2x00dev, 81, 0x3A);
6997 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
6998 rt2800_bbp_write(rt2x00dev, 83, 0x9A);
6999 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
7000 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7001 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7002 rt2800_bbp_write(rt2x00dev, 91, 0x04);
7003 rt2800_bbp_write(rt2x00dev, 92, 0x02);
7004 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
7005 rt2800_bbp_write(rt2x00dev, 96, 0x00);
7006 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
7007 rt2800_bbp_write(rt2x00dev, 104, 0x92);
7009 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
7010 rt2800_bbp_write(rt2x00dev, 106, 0x12);
7011 rt2800_bbp_write(rt2x00dev, 109, 0x00);
7012 rt2800_bbp_write(rt2x00dev, 134, 0x10);
7013 rt2800_bbp_write(rt2x00dev, 135, 0xA6);
7014 rt2800_bbp_write(rt2x00dev, 137, 0x04);
7015 rt2800_bbp_write(rt2x00dev, 142, 0x30);
7016 rt2800_bbp_write(rt2x00dev, 143, 0xF7);
7017 rt2800_bbp_write(rt2x00dev, 160, 0xEC);
7018 rt2800_bbp_write(rt2x00dev, 161, 0xC4);
7019 rt2800_bbp_write(rt2x00dev, 162, 0x77);
7020 rt2800_bbp_write(rt2x00dev, 163, 0xF9);
7021 rt2800_bbp_write(rt2x00dev, 164, 0x00);
7022 rt2800_bbp_write(rt2x00dev, 165, 0x00);
7023 rt2800_bbp_write(rt2x00dev, 186, 0x00);
7024 rt2800_bbp_write(rt2x00dev, 187, 0x00);
7025 rt2800_bbp_write(rt2x00dev, 188, 0x00);
7026 rt2800_bbp_write(rt2x00dev, 186, 0x00);
7027 rt2800_bbp_write(rt2x00dev, 187, 0x01);
7028 rt2800_bbp_write(rt2x00dev, 188, 0x00);
7029 rt2800_bbp_write(rt2x00dev, 189, 0x00);
7031 rt2800_bbp_write(rt2x00dev, 91, 0x06);
7032 rt2800_bbp_write(rt2x00dev, 92, 0x04);
7033 rt2800_bbp_write(rt2x00dev, 93, 0x54);
7034 rt2800_bbp_write(rt2x00dev, 99, 0x50);
7035 rt2800_bbp_write(rt2x00dev, 148, 0x84);
7036 rt2800_bbp_write(rt2x00dev, 167, 0x80);
7037 rt2800_bbp_write(rt2x00dev, 178, 0xFF);
7038 rt2800_bbp_write(rt2x00dev, 106, 0x13);
7041 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
7042 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
7043 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
7044 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
7045 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
7046 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
7047 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
7048 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
7049 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
7050 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
7051 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
7052 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
7053 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
7054 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
7055 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
7056 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
7057 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
7058 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
7059 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
7060 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
7061 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
7062 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
7063 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
7064 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
7065 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
7066 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
7067 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
7068 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
7069 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
7070 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
7071 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
7072 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
7073 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
7074 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
7075 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
7076 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
7077 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
7078 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
7079 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
7080 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
7081 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
7082 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
7083 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
7084 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
7085 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
7086 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
7087 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
7088 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
7089 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
7090 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
7091 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
7092 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
7093 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
7094 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
7095 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
7096 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
7097 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
7098 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
7099 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
7100 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
7101 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
7102 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
7103 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
7104 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
7105 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
7106 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
7107 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
7108 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
7109 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
7110 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
7111 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
7112 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
7113 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
7114 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
7115 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
7116 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
7117 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
7118 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
7119 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
7120 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
7121 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
7122 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
7123 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
7126 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
7127 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
7128 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
7129 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
7130 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
7131 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
7132 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
7133 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
7134 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
7135 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
7136 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
7137 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
7138 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
7139 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
7140 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
7141 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
7142 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
7143 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
7144 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
7145 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
7147 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7150 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
7157 if (rt2800_is_305x_soc(rt2x00dev))
7158 rt2800_init_bbp_305x_soc(rt2x00dev);
7160 switch (rt2x00dev->chip.rt) {
7164 rt2800_init_bbp_28xx(rt2x00dev);
7169 rt2800_init_bbp_30xx(rt2x00dev);
7172 rt2800_init_bbp_3290(rt2x00dev);
7176 rt2800_init_bbp_3352(rt2x00dev);
7179 rt2800_init_bbp_3390(rt2x00dev);
7182 rt2800_init_bbp_3572(rt2x00dev);
7185 rt2800_init_bbp_3593(rt2x00dev);
7188 rt2800_init_bbp_3883(rt2x00dev);
7192 rt2800_init_bbp_53xx(rt2x00dev);
7195 rt2800_init_bbp_5592(rt2x00dev);
7198 rt2800_init_bbp_6352(rt2x00dev);
7203 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
7209 rt2800_bbp_write(rt2x00dev, reg_id, value);
7214 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
7218 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
7220 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
7223 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
7234 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7236 bbp = rt2800_bbp_read(rt2x00dev, 4);
7238 rt2800_bbp_write(rt2x00dev, 4, bbp);
7240 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
7242 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
7244 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7246 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7251 rt2800_bbp_write(rt2x00dev, 24, 0);
7254 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7257 passband = rt2800_bbp_read(rt2x00dev, 55);
7265 rt2800_bbp_write(rt2x00dev, 24, 0x06);
7268 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7271 stopband = rt2800_bbp_read(rt2x00dev, 55);
7279 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7284 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7288 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
7293 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
7295 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7298 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7301 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
7303 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7311 if (rt2x00_rt(rt2x00dev, RT3070)) {
7320 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
7322 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
7327 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7328 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7333 rt2800_bbp_write(rt2x00dev, 24, 0);
7335 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7337 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7342 bbp = rt2800_bbp_read(rt2x00dev, 4);
7344 rt2800_bbp_write(rt2x00dev, 4, bbp);
7347 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
7349 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7353 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
7356 if (rt2x00_rt(rt2x00dev, RT3070) ||
7357 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7358 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
7359 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7360 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
7364 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
7370 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
7372 if (rt2x00_rt(rt2x00dev, RT3090)) {
7374 bbp = rt2800_bbp_read(rt2x00dev, 138);
7375 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7380 rt2800_bbp_write(rt2x00dev, 138, bbp);
7383 if (rt2x00_rt(rt2x00dev, RT3070)) {
7384 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
7385 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
7392 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
7393 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7394 rt2x00_rt(rt2x00dev, RT3090) ||
7395 rt2x00_rt(rt2x00dev, RT3390)) {
7396 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7402 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7404 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
7406 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
7408 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
7410 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
7412 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
7414 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
7418 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
7420 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7424 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
7426 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7428 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
7432 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
7434 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
7436 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
7438 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
7440 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
7442 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7445 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7447 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
7449 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
7454 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
7460 reg = rt2800_bbp_read(rt2x00dev, 138);
7461 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7466 rt2800_bbp_write(rt2x00dev, 138, reg);
7468 reg = rt2800_rfcsr_read(rt2x00dev, 38);
7470 rt2800_rfcsr_write(rt2x00dev, 38, reg);
7472 reg = rt2800_rfcsr_read(rt2x00dev, 39);
7474 rt2800_rfcsr_write(rt2x00dev, 39, reg);
7476 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7478 reg = rt2800_rfcsr_read(rt2x00dev, 30);
7480 rt2800_rfcsr_write(rt2x00dev, 30, reg);
7483 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
7485 rt2800_rf_init_calibration(rt2x00dev, 30);
7487 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
7488 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
7489 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
7490 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
7491 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7492 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7493 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7494 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
7495 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
7496 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7497 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
7498 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7499 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
7500 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
7501 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7502 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7503 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7504 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7505 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7506 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7507 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7508 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7509 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7510 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
7511 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7512 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
7513 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
7514 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
7515 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
7516 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
7517 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
7518 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
7521 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
7528 rt2800_rf_init_calibration(rt2x00dev, 30);
7530 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7531 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7532 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7533 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
7534 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7535 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
7536 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7537 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
7538 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7539 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7540 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7541 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7542 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7543 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7544 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7545 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7546 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7547 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
7548 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
7550 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
7551 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7554 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7555 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7556 rt2x00_rt(rt2x00dev, RT3090)) {
7557 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
7559 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7561 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7563 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7565 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7566 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
7567 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7573 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7575 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7577 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7580 rt2800_rx_filter_calibration(rt2x00dev);
7582 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
7583 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7584 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
7585 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7587 rt2800_led_open_drain_enable(rt2x00dev);
7588 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7591 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7595 rt2800_rf_init_calibration(rt2x00dev, 2);
7597 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7598 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7599 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7600 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7601 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7602 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7603 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7604 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7605 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7606 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7607 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7608 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7609 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7610 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7611 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7612 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7613 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7614 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7615 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7616 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7617 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7618 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7619 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7620 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7621 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7622 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7623 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7624 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7625 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7626 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7627 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7628 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7629 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7630 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7631 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7632 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7633 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7634 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7635 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7636 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7637 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7638 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7639 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7640 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7641 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7642 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7644 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7646 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7648 rt2800_led_open_drain_enable(rt2x00dev);
7649 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7652 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7655 &rt2x00dev->cap_flags);
7657 &rt2x00dev->cap_flags);
7660 rt2800_rf_init_calibration(rt2x00dev, 30);
7662 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7663 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7664 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7665 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7666 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7667 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7668 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7669 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7670 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7671 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7672 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7673 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7674 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7675 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7676 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7677 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7678 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7679 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7680 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7681 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7682 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7683 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7684 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7685 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7686 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7687 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7688 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7689 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7690 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7691 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7692 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7693 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7694 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7700 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7701 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7702 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7703 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7704 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7705 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7706 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7712 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7718 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7719 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7720 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7721 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7722 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7723 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7724 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7725 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7731 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7732 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7733 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7734 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7735 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7736 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7737 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7738 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7739 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7740 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7741 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7742 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7743 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7744 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7746 rt2800_rx_filter_calibration(rt2x00dev);
7747 rt2800_led_open_drain_enable(rt2x00dev);
7748 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7751 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7755 rt2800_rf_init_calibration(rt2x00dev, 30);
7757 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7758 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7759 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7760 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7761 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7762 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7763 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7764 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7765 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7766 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7767 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7768 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7769 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7770 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7771 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7772 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7773 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7774 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7775 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7776 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7777 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7778 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7779 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7780 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7781 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7782 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7783 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7784 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7785 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7786 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7787 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7788 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7790 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7792 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7794 rt2800_rx_filter_calibration(rt2x00dev);
7796 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7797 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7799 rt2800_led_open_drain_enable(rt2x00dev);
7800 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7803 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7808 rt2800_rf_init_calibration(rt2x00dev, 30);
7810 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7811 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7812 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7813 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7814 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7815 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7816 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7817 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7818 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7819 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7820 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7821 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7822 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7823 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7824 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7825 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7826 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7827 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7828 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7829 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7830 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7831 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7832 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7833 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7834 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7835 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7836 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7837 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7838 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7839 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7840 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7842 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7844 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7846 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7849 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7851 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7854 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7856 rt2800_rx_filter_calibration(rt2x00dev);
7857 rt2800_led_open_drain_enable(rt2x00dev);
7858 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7861 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7866 bbp = rt2800_bbp_read(rt2x00dev, 105);
7867 if (rt2x00dev->default_ant.rx_chain_num == 1)
7871 rt2800_bbp_write(rt2x00dev, 105, bbp);
7873 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7875 rt2800_bbp_write(rt2x00dev, 92, 0x02);
7876 rt2800_bbp_write(rt2x00dev, 82, 0x82);
7877 rt2800_bbp_write(rt2x00dev, 106, 0x05);
7878 rt2800_bbp_write(rt2x00dev, 104, 0x92);
7879 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7880 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7881 rt2800_bbp_write(rt2x00dev, 47, 0x48);
7882 rt2800_bbp_write(rt2x00dev, 120, 0x50);
7885 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7887 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7890 rt2800_bbp_write(rt2x00dev, 142, 6);
7891 rt2800_bbp_write(rt2x00dev, 143, 160);
7892 rt2800_bbp_write(rt2x00dev, 142, 7);
7893 rt2800_bbp_write(rt2x00dev, 143, 161);
7894 rt2800_bbp_write(rt2x00dev, 142, 8);
7895 rt2800_bbp_write(rt2x00dev, 143, 162);
7898 rt2800_bbp_write(rt2x00dev, 31, 0x08);
7901 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7904 rt2800_bbp_write(rt2x00dev, 105, 0x04);
7908 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7910 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7915 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7918 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7921 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7922 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7923 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7924 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7925 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7926 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7927 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7928 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7929 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7930 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7931 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7932 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7933 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7934 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7935 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7936 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7937 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7938 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7939 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7940 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7941 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7942 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
7943 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
7944 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
7945 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
7946 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
7947 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
7948 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
7949 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
7950 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
7951 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
7952 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
7956 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
7958 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
7960 rt2800_freq_cal_mode1(rt2x00dev);
7962 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
7964 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
7966 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7969 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7971 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7973 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7980 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7981 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7983 rt2800_led_open_drain_enable(rt2x00dev);
7984 rt2800_normal_mode_setup_3593(rt2x00dev);
7986 rt3593_post_bbp_init(rt2x00dev);
7991 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
7993 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7994 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7995 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7996 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7997 rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
7998 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7999 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8000 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8001 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
8002 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
8003 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8004 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8005 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8006 if (rt2800_clk_is_20mhz(rt2x00dev))
8007 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
8009 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8010 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8011 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8012 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
8013 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8014 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8015 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8016 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8017 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8018 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8019 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8020 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8021 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8022 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8023 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8024 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
8025 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8026 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8027 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8028 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8029 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8030 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8031 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8032 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8033 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8034 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8035 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8036 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8037 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8038 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8039 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
8040 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
8041 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8042 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8043 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8044 rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
8045 rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
8046 rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
8047 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8048 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8049 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8050 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8051 rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
8052 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8053 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8054 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
8055 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8056 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8057 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8058 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8061 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
8068 rt2800_rf_init_calibration(rt2x00dev, 2);
8070 rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
8071 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8072 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8073 rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
8074 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
8075 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
8076 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
8077 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8078 rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
8079 rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
8080 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
8081 rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
8082 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
8083 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
8084 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8085 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8086 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8092 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
8093 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8094 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8095 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8096 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8097 rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
8098 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8099 rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8100 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8101 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8102 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8103 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
8104 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8105 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8106 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8107 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8108 rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
8109 rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8110 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8111 rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8112 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8113 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8114 rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8115 rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
8116 rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
8117 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8118 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
8119 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8120 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8121 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8122 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
8123 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8124 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8125 rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
8126 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
8127 rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
8128 rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
8129 rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
8130 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8131 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
8132 rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
8133 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
8134 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
8135 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
8136 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8137 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8141 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
8143 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
8145 rt2800_bbp_write(rt2x00dev, 105, 0x05);
8147 rt2800_bbp_write(rt2x00dev, 179, 0x02);
8148 rt2800_bbp_write(rt2x00dev, 180, 0x00);
8149 rt2800_bbp_write(rt2x00dev, 182, 0x40);
8150 rt2800_bbp_write(rt2x00dev, 180, 0x01);
8151 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
8153 rt2800_bbp_write(rt2x00dev, 179, 0x00);
8155 rt2800_bbp_write(rt2x00dev, 142, 0x04);
8156 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
8157 rt2800_bbp_write(rt2x00dev, 142, 0x06);
8158 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
8159 rt2800_bbp_write(rt2x00dev, 142, 0x07);
8160 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
8161 rt2800_bbp_write(rt2x00dev, 142, 0x08);
8162 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
8163 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
8166 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
8167 rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
8170 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8173 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8176 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8178 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
8180 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
8182 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
8184 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
8186 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
8188 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
8190 rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
8192 rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
8194 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
8196 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
8199 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
8201 rt2800_rf_init_calibration(rt2x00dev, 2);
8203 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
8204 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8205 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8206 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8207 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8208 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8210 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
8211 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8212 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8213 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8214 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8215 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8216 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8217 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8218 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8219 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8220 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8222 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8223 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8224 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8225 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8226 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8227 if (rt2x00_is_usb(rt2x00dev) &&
8228 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8229 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8231 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
8232 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8233 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8234 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8235 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8237 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8238 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8239 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8240 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8241 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8242 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8243 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8244 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8245 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8246 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8248 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8249 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8250 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
8251 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
8252 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8253 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8254 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8255 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8257 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
8258 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8259 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8260 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8262 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8263 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8264 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8266 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
8267 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
8268 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
8269 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8270 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
8272 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
8273 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
8274 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
8275 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
8277 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8278 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
8279 if (rt2x00_is_usb(rt2x00dev))
8280 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8282 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
8284 if (rt2x00_is_usb(rt2x00dev))
8285 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
8287 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
8289 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8290 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8292 rt2800_normal_mode_setup_5xxx(rt2x00dev);
8294 rt2800_led_open_drain_enable(rt2x00dev);
8297 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
8299 rt2800_rf_init_calibration(rt2x00dev, 2);
8301 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
8302 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8303 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8304 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8305 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8306 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8307 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8308 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8309 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8310 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8311 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8312 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8313 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8314 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
8315 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8316 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
8317 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8318 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
8319 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
8320 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8321 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8322 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8323 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8324 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8325 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8326 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8327 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
8328 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8329 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8330 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8331 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8332 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8333 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
8334 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8335 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
8336 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8337 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8338 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8339 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8340 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8341 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8342 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
8343 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8344 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8345 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
8346 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
8347 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
8348 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
8349 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8350 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8351 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
8352 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8353 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8354 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
8355 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8356 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
8357 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
8358 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8360 rt2800_normal_mode_setup_5xxx(rt2x00dev);
8362 rt2800_led_open_drain_enable(rt2x00dev);
8365 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
8367 rt2800_rf_init_calibration(rt2x00dev, 30);
8369 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
8370 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8371 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8372 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
8373 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8374 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8375 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8376 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8377 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8378 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
8379 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
8380 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
8381 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8382 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8383 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8384 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8385 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8386 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8387 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
8388 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
8389 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8391 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8394 rt2800_freq_cal_mode1(rt2x00dev);
8397 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
8398 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
8400 rt2800_normal_mode_setup_5xxx(rt2x00dev);
8402 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
8403 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8405 rt2800_led_open_drain_enable(rt2x00dev);
8408 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
8413 bbp_val = rt2800_bbp_read(rt2x00dev, 21);
8415 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
8419 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8421 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8425 bbp_val = rt2800_bbp_read(rt2x00dev, 21);
8427 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
8431 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
8436 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
8438 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
8440 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
8442 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8444 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
8447 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
8448 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
8449 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
8450 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8453 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
8454 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8457 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
8458 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
8460 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
8461 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
8462 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
8463 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8466 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
8467 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8470 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
8476 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
8482 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
8487 bbp_val = rt2800_bbp_read(rt2x00dev, 159);
8494 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
8502 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
8505 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8523 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8524 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8527 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
8529 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
8530 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8533 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8534 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8535 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8536 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8537 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
8538 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8539 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8540 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8541 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8542 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8543 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8544 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8546 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
8547 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
8548 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
8549 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
8550 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
8551 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
8552 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
8553 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
8554 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
8555 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
8557 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8558 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8560 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8562 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
8564 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8566 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
8571 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8577 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8580 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
8583 bbp_val = rt2800_bbp_read(rt2x00dev, 23);
8586 rt2800_bbp_write(rt2x00dev, 23, bbp_val);
8606 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8611 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
8613 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
8615 rt2800_rf_lp_config(rt2x00dev, btxcal);
8618 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8620 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8621 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8623 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8626 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8628 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8629 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8631 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8636 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8638 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8640 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8642 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8644 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8646 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8649 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8652 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8653 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8656 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8658 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8661 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8662 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8665 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8670 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8672 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8710 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
8711 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
8712 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
8713 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
8714 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
8715 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
8716 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
8717 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
8718 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
8719 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
8720 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
8721 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
8723 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
8724 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
8725 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
8726 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
8727 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
8728 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
8729 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
8730 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
8731 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
8732 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
8734 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
8735 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
8737 rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
8739 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
8740 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
8742 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8744 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
8745 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8747 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8748 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8751 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
8754 rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
8755 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8756 rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
8757 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
8758 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
8759 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
8760 rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
8761 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8762 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
8763 rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
8764 rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
8765 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
8766 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
8767 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8768 rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
8769 rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
8770 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
8771 rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
8772 rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
8773 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8774 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
8775 rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
8776 rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
8777 rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
8778 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
8779 rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
8780 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
8781 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8782 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8783 rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
8784 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
8785 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
8786 rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
8787 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8788 rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
8789 rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8790 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8791 rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8792 rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
8793 rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
8794 rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8795 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
8796 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
8797 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8799 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
8800 if (rt2800_clk_is_20mhz(rt2x00dev))
8801 rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
8803 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8804 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
8805 rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
8806 rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
8807 rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
8808 rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
8809 rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
8810 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
8811 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
8812 rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
8813 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8814 rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8815 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
8816 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8817 rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
8818 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
8819 rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
8821 rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
8822 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
8823 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
8826 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
8827 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
8828 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
8829 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
8830 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
8831 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
8832 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
8833 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
8834 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
8835 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
8836 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
8837 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8838 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
8839 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
8840 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8841 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
8842 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
8843 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
8844 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
8845 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8846 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
8847 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
8848 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
8849 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
8850 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
8851 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
8852 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
8853 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
8854 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
8855 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
8856 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
8857 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
8858 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
8859 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
8860 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
8861 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
8862 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
8863 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
8864 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
8865 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
8866 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
8867 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
8868 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
8869 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
8870 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
8871 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8872 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
8873 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
8874 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
8875 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
8876 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
8877 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
8878 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
8879 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
8880 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
8881 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
8882 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
8883 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
8884 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
8885 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
8887 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
8889 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
8890 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
8891 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
8892 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
8893 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
8894 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
8895 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
8896 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
8897 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
8898 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
8899 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
8900 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
8901 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
8902 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
8903 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8904 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
8905 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8906 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
8907 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
8908 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
8909 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
8910 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
8911 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
8912 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8913 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
8914 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
8915 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
8916 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8917 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
8918 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
8920 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
8921 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8922 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8923 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
8924 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
8925 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
8926 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
8927 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8928 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
8930 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
8931 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
8932 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
8933 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
8934 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8935 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8938 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8939 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
8940 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
8941 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
8942 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
8943 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
8944 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
8945 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
8948 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
8949 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
8950 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
8951 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
8952 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
8953 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8954 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
8955 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
8956 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
8957 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
8958 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
8959 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
8960 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
8961 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
8962 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
8963 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
8964 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
8965 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
8966 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
8967 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
8968 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8969 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
8970 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
8971 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
8972 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
8973 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
8974 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
8975 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
8976 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
8977 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
8978 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
8979 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
8980 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
8981 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
8982 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
8983 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
8984 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
8985 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
8986 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
8987 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
8988 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
8989 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
8990 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
8991 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
8992 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
8993 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
8994 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
8995 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
8996 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
8997 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
8998 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
8999 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
9000 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
9001 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
9002 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
9003 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
9004 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
9005 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
9006 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
9008 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
9009 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
9010 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
9012 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
9013 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
9015 rt2800_bw_filter_calibration(rt2x00dev, true);
9016 rt2800_bw_filter_calibration(rt2x00dev, false);
9019 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
9021 if (rt2800_is_305x_soc(rt2x00dev)) {
9022 rt2800_init_rfcsr_305x_soc(rt2x00dev);
9026 switch (rt2x00dev->chip.rt) {
9030 rt2800_init_rfcsr_30xx(rt2x00dev);
9033 rt2800_init_rfcsr_3290(rt2x00dev);
9036 rt2800_init_rfcsr_3352(rt2x00dev);
9039 rt2800_init_rfcsr_3390(rt2x00dev);
9042 rt2800_init_rfcsr_3883(rt2x00dev);
9045 rt2800_init_rfcsr_3572(rt2x00dev);
9048 rt2800_init_rfcsr_3593(rt2x00dev);
9051 rt2800_init_rfcsr_5350(rt2x00dev);
9054 rt2800_init_rfcsr_5390(rt2x00dev);
9057 rt2800_init_rfcsr_5392(rt2x00dev);
9060 rt2800_init_rfcsr_5592(rt2x00dev);
9063 rt2800_init_rfcsr_6352(rt2x00dev);
9068 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
9076 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
9077 rt2800_init_registers(rt2x00dev)))
9083 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
9089 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
9090 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
9091 if (rt2x00_is_usb(rt2x00dev))
9092 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
9093 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
9099 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
9105 rt2800_init_bbp(rt2x00dev);
9106 rt2800_init_rfcsr(rt2x00dev);
9108 if (rt2x00_is_usb(rt2x00dev) &&
9109 (rt2x00_rt(rt2x00dev, RT3070) ||
9110 rt2x00_rt(rt2x00dev, RT3071) ||
9111 rt2x00_rt(rt2x00dev, RT3572))) {
9113 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
9120 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9123 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9127 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
9131 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
9133 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9136 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9141 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
9142 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
9145 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
9146 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
9149 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
9150 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
9157 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
9161 rt2800_disable_wpdma(rt2x00dev);
9164 rt2800_wait_wpdma_ready(rt2x00dev);
9166 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9169 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9173 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
9178 if (rt2x00_rt(rt2x00dev, RT3290))
9183 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
9188 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
9197 if (rt2x00_rt(rt2x00dev, RT3290)) {
9210 mutex_lock(&rt2x00dev->csr_mutex);
9212 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
9216 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
9219 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®);
9221 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
9223 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
9224 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
9225 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
9226 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
9227 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
9228 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
9229 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
9231 mutex_unlock(&rt2x00dev->csr_mutex);
9234 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
9239 rt2800_efuse_read(rt2x00dev, i);
9245 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
9249 if (rt2x00_rt(rt2x00dev, RT3593) ||
9250 rt2x00_rt(rt2x00dev, RT3883))
9253 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
9260 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
9264 if (rt2x00_rt(rt2x00dev, RT3593) ||
9265 rt2x00_rt(rt2x00dev, RT3883))
9268 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
9275 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
9277 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
9286 retval = rt2800_read_eeprom(rt2x00dev);
9293 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
9294 rt2x00lib_set_mac_address(rt2x00dev, mac);
9296 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
9301 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
9302 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
9303 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
9304 rt2x00_rt(rt2x00dev, RT2872)) {
9310 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
9313 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9330 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
9331 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
9334 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
9337 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
9338 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
9344 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
9345 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
9346 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
9347 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
9348 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
9356 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
9359 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
9364 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
9366 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
9368 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
9371 if (!rt2x00_rt(rt2x00dev, RT3593) &&
9372 !rt2x00_rt(rt2x00dev, RT3883)) {
9378 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
9380 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
9382 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
9387 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
9389 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
9392 if (!rt2x00_rt(rt2x00dev, RT3593) &&
9393 !rt2x00_rt(rt2x00dev, RT3883)) {
9399 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
9401 if (rt2x00_rt(rt2x00dev, RT3593) ||
9402 rt2x00_rt(rt2x00dev, RT3883)) {
9403 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
9412 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
9418 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
9427 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
9434 if (rt2x00_rt(rt2x00dev, RT3290) ||
9435 rt2x00_rt(rt2x00dev, RT5390) ||
9436 rt2x00_rt(rt2x00dev, RT5392) ||
9437 rt2x00_rt(rt2x00dev, RT6352))
9438 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
9439 else if (rt2x00_rt(rt2x00dev, RT3352))
9441 else if (rt2x00_rt(rt2x00dev, RT3883))
9443 else if (rt2x00_rt(rt2x00dev, RT5350))
9475 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
9480 rt2x00_set_rf(rt2x00dev, rf);
9485 rt2x00dev->default_ant.tx_chain_num =
9487 rt2x00dev->default_ant.rx_chain_num =
9490 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9492 if (rt2x00_rt(rt2x00dev, RT3070) ||
9493 rt2x00_rt(rt2x00dev, RT3090) ||
9494 rt2x00_rt(rt2x00dev, RT3352) ||
9495 rt2x00_rt(rt2x00dev, RT3390)) {
9502 rt2x00dev->default_ant.tx = ANTENNA_A;
9503 rt2x00dev->default_ant.rx = ANTENNA_A;
9506 rt2x00dev->default_ant.tx = ANTENNA_A;
9507 rt2x00dev->default_ant.rx = ANTENNA_B;
9511 rt2x00dev->default_ant.tx = ANTENNA_A;
9512 rt2x00dev->default_ant.rx = ANTENNA_A;
9516 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
9517 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
9518 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
9519 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
9526 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
9528 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
9534 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
9539 if (!rt2x00_rt(rt2x00dev, RT3352) &&
9541 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
9546 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
9547 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
9553 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
9554 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
9555 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
9557 rt2x00dev->led_mcu_reg = eeprom;
9563 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
9567 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
9572 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9574 if (rt2x00_rt(rt2x00dev, RT3352)) {
9578 &rt2x00dev->cap_flags);
9582 &rt2x00dev->cap_flags);
9959 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
9961 struct hw_mode_spec *spec = &rt2x00dev->spec;
9972 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
9978 rt2x00dev->hw->wiphy->retry_short = 2;
9979 rt2x00dev->hw->wiphy->retry_long = 2;
9984 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
9985 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
9986 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
9987 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
9988 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9997 if (!rt2x00_is_usb(rt2x00dev))
9998 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
10000 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
10002 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
10003 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
10004 rt2800_eeprom_addr(rt2x00dev,
10016 rt2x00dev->hw->max_rates = 1;
10017 rt2x00dev->hw->max_report_rates = 7;
10018 rt2x00dev->hw->max_rate_tries = 1;
10025 switch (rt2x00dev->chip.rf) {
10054 if (rt2800_clk_is_20mhz(rt2x00dev))
10077 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
10098 if (!rt2x00_rf(rt2x00dev, RF2020))
10109 tx_chains = rt2x00dev->default_ant.tx_chain_num;
10110 rx_chains = rt2x00dev->default_ant.rx_chain_num;
10148 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
10149 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
10151 if (rt2x00dev->default_ant.tx_chain_num > 2)
10152 default_power3 = rt2800_eeprom_addr(rt2x00dev,
10165 default_power1 = rt2800_eeprom_addr(rt2x00dev,
10167 default_power2 = rt2800_eeprom_addr(rt2x00dev,
10170 if (rt2x00dev->default_ant.tx_chain_num > 2)
10172 rt2800_eeprom_addr(rt2x00dev,
10185 switch (rt2x00dev->chip.rf) {
10205 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
10212 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
10218 if (rt2x00_rt(rt2x00dev, RT3290))
10219 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
10221 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
10245 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
10250 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
10253 rt2x00_set_rt(rt2x00dev, rt, rev);
10258 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
10263 retval = rt2800_probe_rt(rt2x00dev);
10270 retval = rt2800_validate_eeprom(rt2x00dev);
10274 retval = rt2800_init_eeprom(rt2x00dev);
10282 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
10284 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
10289 retval = rt2800_probe_hw_mode(rt2x00dev);
10296 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
10297 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
10298 if (!rt2x00_is_usb(rt2x00dev))
10299 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
10304 if (!rt2x00_is_soc(rt2x00dev))
10305 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
10306 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
10307 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
10308 if (!rt2800_hwcrypt_disabled(rt2x00dev))
10309 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
10310 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
10311 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
10312 if (rt2x00_is_usb(rt2x00dev))
10313 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
10315 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
10316 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
10320 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags);
10321 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100);
10323 rt2x00dev->link.watchdog_disabled = true;
10329 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
10342 struct rt2x00_dev *rt2x00dev = hw->priv;
10350 rt2800_register_multiread(rt2x00dev, offset,
10360 struct rt2x00_dev *rt2x00dev = hw->priv;
10364 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
10366 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
10368 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
10370 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
10372 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
10374 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
10376 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
10378 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
10380 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
10382 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
10384 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
10386 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
10388 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
10390 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
10400 struct rt2x00_dev *rt2x00dev = hw->priv;
10424 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
10431 reg = rt2800_register_read(rt2x00dev, offset);
10433 rt2800_register_write(rt2x00dev, offset, reg);
10439 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
10441 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
10443 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
10445 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
10447 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
10449 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
10454 reg = rt2800_register_read(rt2x00dev, offset);
10459 rt2800_register_write(rt2x00dev, offset, reg);
10467 struct rt2x00_dev *rt2x00dev = hw->priv;
10471 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
10473 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
10531 struct rt2x00_dev *rt2x00dev = hw->priv;
10540 idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
10541 busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
10542 busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);