Lines Matching refs:rt2x00dev
45 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
50 mutex_lock(&rt2x00dev->csr_mutex);
56 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
66 mutex_unlock(&rt2x00dev->csr_mutex);
69 static u8 rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
75 mutex_lock(&rt2x00dev->csr_mutex);
85 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
91 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
93 WAIT_FOR_BBP(rt2x00dev, ®);
98 mutex_unlock(&rt2x00dev->csr_mutex);
103 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
108 mutex_lock(&rt2x00dev->csr_mutex);
114 if (WAIT_FOR_RF(rt2x00dev, ®)) {
121 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
122 rt2x00_rf_write(rt2x00dev, word, value);
125 mutex_unlock(&rt2x00dev->csr_mutex);
130 struct rt2x00_dev *rt2x00dev = eeprom->data;
133 reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
145 struct rt2x00_dev *rt2x00dev = eeprom->data;
155 rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
193 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
197 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
210 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
217 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
228 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
231 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
236 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
240 led->rt2x00dev = rt2x00dev;
251 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
262 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
270 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
272 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
273 !rt2x00dev->intf_ap_count);
278 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
281 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
286 struct data_queue *queue = rt2x00dev->bcn;
295 reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1);
298 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
303 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
305 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
309 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
313 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
317 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
330 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1);
335 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
337 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2);
342 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
344 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3);
349 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
351 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4);
356 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
358 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5);
363 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
367 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
370 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
372 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
374 reg = rt2x00mmio_register_read(rt2x00dev, CSR18);
377 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
379 reg = rt2x00mmio_register_read(rt2x00dev, CSR19);
382 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
386 reg = rt2x00mmio_register_read(rt2x00dev, CSR12);
391 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
396 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
410 reg = rt2x00mmio_register_read(rt2x00dev, BBPCSR1);
411 r14 = rt2500pci_bbp_read(rt2x00dev, 14);
412 r2 = rt2500pci_bbp_read(rt2x00dev, 2);
447 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
455 if (rt2x00_rf(rt2x00dev, RF2525E))
462 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg);
463 rt2500pci_bbp_write(rt2x00dev, 14, r14);
464 rt2500pci_bbp_write(rt2x00dev, 2, r2);
467 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
481 if (!rt2x00_rf(rt2x00dev, RF2523))
488 if (rt2x00_rf(rt2x00dev, RF2525)) {
496 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
497 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
498 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
500 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
503 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
504 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
505 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
507 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
514 rt2500pci_bbp_write(rt2x00dev, 70, r70);
522 if (!rt2x00_rf(rt2x00dev, RF2523)) {
524 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
528 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
533 rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0);
536 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
541 rf3 = rt2x00_rf_read(rt2x00dev, 3);
543 rt2500pci_rf_write(rt2x00dev, 3, rf3);
546 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
551 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
556 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
559 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
568 reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
570 (rt2x00dev->beacon_int - 20) * 16);
576 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
579 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
581 reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
583 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
586 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
589 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
594 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
598 rt2500pci_config_txpower(rt2x00dev,
601 rt2500pci_config_retry_limit(rt2x00dev, libconf);
603 rt2500pci_config_ps(rt2x00dev, libconf);
609 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
617 reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
623 reg = rt2x00mmio_register_read(rt2x00dev, CNT3);
627 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
631 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
637 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
640 rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
643 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
651 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
652 rt2x00dev->intf_associated && count > 20)
661 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
662 !rt2x00dev->intf_associated)
672 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
680 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
688 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
697 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
708 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
710 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
718 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
723 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
725 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
728 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
732 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
741 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
746 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
748 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
751 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
753 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
756 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
758 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
767 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
774 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
776 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
779 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
781 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
784 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
788 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
793 tasklet_kill(&rt2x00dev->tbtt_tasklet);
842 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
850 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2);
851 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
852 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
853 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
854 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
855 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
857 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
858 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3);
861 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
863 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
864 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5);
867 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
869 entry_priv = rt2x00dev->atim->entries[0].priv_data;
870 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4);
873 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
875 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
876 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6);
879 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
881 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1);
882 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
883 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
884 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
886 entry_priv = rt2x00dev->rx->entries[0].priv_data;
887 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2);
890 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
895 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
899 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
900 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
901 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00020002);
902 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
904 reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR);
908 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
910 reg = rt2x00mmio_register_read(rt2x00dev, CSR9);
912 rt2x00dev->rx->data_size / 128);
913 rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
918 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
920 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
922 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
931 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
933 rt2x00mmio_register_write(rt2x00dev, CNT3, 0);
935 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR8);
944 rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg);
946 reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR0);
951 rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg);
953 reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR1);
958 rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg);
960 reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR2);
965 rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg);
967 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3);
976 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
978 reg = rt2x00mmio_register_read(rt2x00dev, PCICSR);
986 rt2x00mmio_register_write(rt2x00dev, PCICSR, reg);
988 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
990 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
991 rt2x00mmio_register_write(rt2x00dev, TESTCSR, 0x000000f0);
993 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
996 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00213223);
997 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
999 reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2);
1001 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
1003 reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR);
1010 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
1012 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, 0x82188200);
1014 rt2x00mmio_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
1016 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
1020 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
1022 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
1025 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
1032 reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
1033 reg = rt2x00mmio_register_read(rt2x00dev, CNT4);
1038 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1044 value = rt2500pci_bbp_read(rt2x00dev, 0);
1050 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
1054 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1061 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
1064 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1065 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1066 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1067 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1068 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1069 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1070 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1071 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1072 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1073 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1074 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1075 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1076 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1077 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1078 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1079 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1080 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1081 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1082 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1083 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1084 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1085 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1086 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1087 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1088 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1089 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1090 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1091 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1092 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1093 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1096 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
1101 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1111 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1123 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1124 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1131 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1133 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1139 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1141 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1147 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1148 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1149 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1153 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1158 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1159 rt2500pci_init_registers(rt2x00dev) ||
1160 rt2500pci_init_bbp(rt2x00dev)))
1166 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1171 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1174 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1185 reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1190 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1198 reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1203 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1210 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1217 retval = rt2500pci_enable_radio(rt2x00dev);
1220 rt2500pci_disable_radio(rt2x00dev);
1224 rt2500pci_toggle_irq(rt2x00dev, state);
1230 retval = rt2500pci_set_state(rt2x00dev, state);
1238 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1320 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1327 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
1329 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1332 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1344 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1350 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1379 entry->queue->rt2x00dev->rssi_offset;
1393 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1396 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1432 static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1441 spin_lock_irq(&rt2x00dev->irqmask_lock);
1443 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1445 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1447 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1452 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1459 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1460 rt2500pci_txdone(rt2x00dev, QID_AC_VO);
1461 rt2500pci_txdone(rt2x00dev, QID_AC_VI);
1466 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1467 spin_lock_irq(&rt2x00dev->irqmask_lock);
1469 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1473 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1475 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1481 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet);
1482 rt2x00lib_beacondone(rt2x00dev);
1483 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1484 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1489 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1491 if (rt2x00mmio_rxdone(rt2x00dev))
1492 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1493 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1494 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1499 struct rt2x00_dev *rt2x00dev = dev_instance;
1506 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1507 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1512 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1521 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1524 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1529 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1542 spin_lock(&rt2x00dev->irqmask_lock);
1544 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1546 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1548 spin_unlock(&rt2x00dev->irqmask_lock);
1556 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1563 reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
1565 eeprom.data = rt2x00dev;
1575 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1581 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1582 rt2x00lib_set_mac_address(rt2x00dev, mac);
1584 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1596 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1597 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
1600 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC);
1605 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1606 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
1609 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET);
1613 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1614 rt2x00_eeprom_dbg(rt2x00dev, "Calibrate offset: 0x%04x\n",
1621 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1630 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1636 reg = rt2x00mmio_register_read(rt2x00dev, CSR0);
1637 rt2x00_set_chip(rt2x00dev, RT2560, value,
1640 if (!rt2x00_rf(rt2x00dev, RF2522) &&
1641 !rt2x00_rf(rt2x00dev, RF2523) &&
1642 !rt2x00_rf(rt2x00dev, RF2524) &&
1643 !rt2x00_rf(rt2x00dev, RF2525) &&
1644 !rt2x00_rf(rt2x00dev, RF2525E) &&
1645 !rt2x00_rf(rt2x00dev, RF5222)) {
1646 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1653 rt2x00dev->default_ant.tx =
1655 rt2x00dev->default_ant.rx =
1664 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1668 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1676 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1680 __set_bit(REQUIRE_DELAYED_RFKILL, &rt2x00dev->cap_flags);
1686 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC);
1688 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1693 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET);
1694 rt2x00dev->rssi_offset =
1855 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1857 struct hw_mode_spec *spec = &rt2x00dev->spec;
1865 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
1866 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
1867 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
1868 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
1870 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1871 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1872 rt2x00_eeprom_addr(rt2x00dev,
1878 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1886 if (rt2x00_rf(rt2x00dev, RF2522)) {
1889 } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1892 } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1895 } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1898 } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1901 } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1916 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1932 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1940 retval = rt2500pci_validate_eeprom(rt2x00dev);
1944 retval = rt2500pci_init_eeprom(rt2x00dev);
1952 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
1954 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1959 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1966 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1967 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1968 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1973 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1984 struct rt2x00_dev *rt2x00dev = hw->priv;
1988 reg = rt2x00mmio_register_read(rt2x00dev, CSR17);
1990 reg = rt2x00mmio_register_read(rt2x00dev, CSR16);
1998 struct rt2x00_dev *rt2x00dev = hw->priv;
2001 reg = rt2x00mmio_register_read(rt2x00dev, CSR15);