Lines Matching refs:reg
48 u32 reg;
56 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
57 reg = 0;
58 rt2x00_set_field32(®, BBPCSR_VALUE, value);
59 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
60 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
61 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
72 u32 reg;
82 * doesn't become available in time, reg will be 0xffffffff
85 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
86 reg = 0;
87 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
88 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
89 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
91 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
93 WAIT_FOR_BBP(rt2x00dev, ®);
96 value = rt2x00_get_field32(reg, BBPCSR_VALUE);
106 u32 reg;
114 if (WAIT_FOR_RF(rt2x00dev, ®)) {
115 reg = 0;
116 rt2x00_set_field32(®, RFCSR_VALUE, value);
117 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
118 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
119 rt2x00_set_field32(®, RFCSR_BUSY, 1);
121 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
131 u32 reg;
133 reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
135 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
136 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
138 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
140 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
146 u32 reg = 0;
148 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
149 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
150 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
152 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
155 rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
195 u32 reg;
197 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
198 return rt2x00_get_field32(reg, GPIOCSR_VAL0);
208 u32 reg;
210 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
213 rt2x00_set_field32(®, LEDCSR_LINK, enabled);
215 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled);
217 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
226 u32 reg;
228 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
229 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on);
230 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off);
231 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
254 u32 reg;
261 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
262 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
264 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
266 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
268 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
270 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
273 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
274 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
283 u32 reg;
290 reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1);
291 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
292 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
297 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
298 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
299 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
317 u32 reg;
325 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1);
326 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x1ff);
327 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0x13a);
328 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
329 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
330 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
332 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2);
333 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
334 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
335 rt2x00_set_field32(®, ARCSR2_LENGTH,
337 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
339 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3);
340 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
341 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
342 rt2x00_set_field32(®, ARCSR2_LENGTH,
344 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
346 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4);
347 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
348 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
349 rt2x00_set_field32(®, ARCSR2_LENGTH,
351 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
353 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5);
354 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
355 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
356 rt2x00_set_field32(®, ARCSR2_LENGTH,
358 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
365 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
366 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time);
367 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
369 reg = rt2x00mmio_register_read(rt2x00dev, CSR18);
370 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs);
371 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs);
372 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
374 reg = rt2x00mmio_register_read(rt2x00dev, CSR19);
375 rt2x00_set_field32(®, CSR19_DIFS, erp->difs);
376 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs);
377 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
381 reg = rt2x00mmio_register_read(rt2x00dev, CSR12);
382 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
384 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
386 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
501 u32 reg;
503 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
504 rt2x00_set_field32(®, CSR11_LONG_RETRY,
506 rt2x00_set_field32(®, CSR11_SHORT_RETRY,
508 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
517 u32 reg;
520 reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
521 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN,
523 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP,
527 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
528 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
530 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1);
531 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
533 reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
534 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
535 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
559 u32 reg;
561 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
562 rt2x00_set_field32(®, CSR11_CWMIN, cw_min);
563 rt2x00_set_field32(®, CSR11_CWMAX, cw_max);
564 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
573 u32 reg;
579 reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
580 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
630 u32 reg;
634 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
635 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0);
636 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
639 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
640 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
641 rt2x00_set_field32(®, CSR14_TBCN, 1);
642 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
643 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
653 u32 reg;
657 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
658 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1);
659 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
662 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
663 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1);
664 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
667 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
668 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1);
669 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
679 u32 reg;
685 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
686 rt2x00_set_field32(®, TXCSR0_ABORT, 1);
687 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
690 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
691 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1);
692 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
695 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
696 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
697 rt2x00_set_field32(®, CSR14_TBCN, 0);
698 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
699 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
760 u32 reg;
765 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2);
766 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
767 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
768 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
769 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
770 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
773 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3);
774 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
776 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
779 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5);
780 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
782 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
785 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4);
786 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
788 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
791 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6);
792 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
794 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
796 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1);
797 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
798 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
799 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
802 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2);
803 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
805 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
812 u32 reg;
819 reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR);
820 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
821 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
822 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
823 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
825 reg = rt2x00mmio_register_read(rt2x00dev, CSR9);
826 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
828 rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
830 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
831 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
832 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
833 rt2x00_set_field32(®, CSR14_TBCN, 0);
834 rt2x00_set_field32(®, CSR14_TCFP, 0);
835 rt2x00_set_field32(®, CSR14_TATIMW, 0);
836 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
837 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0);
838 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0);
839 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
843 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0);
844 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133);
845 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134);
846 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136);
847 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135);
848 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
850 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3);
851 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/
852 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
853 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */
854 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
855 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */
856 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
857 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
867 reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2);
868 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
869 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
871 reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR);
872 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
873 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154);
874 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
875 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154);
876 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
878 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
879 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
880 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
881 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
882 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
884 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
885 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
886 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
887 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
894 reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
895 reg = rt2x00mmio_register_read(rt2x00dev, CNT4);
961 u32 reg;
969 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
970 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
979 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
980 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
981 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
982 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
983 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
984 rt2x00_set_field32(®, CSR8_RXDONE, mask);
985 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1024 u32 reg, reg2;
1032 reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1033 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
1034 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
1035 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
1036 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1037 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1050 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1169 u32 reg;
1175 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
1176 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
1177 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1186 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1200 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1201 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1307 u32 reg;
1315 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1316 rt2x00_set_field32(®, irq_field, 0);
1317 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1326 u32 reg;
1341 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1342 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0);
1343 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0);
1344 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0);
1345 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1372 u32 reg, mask;
1378 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1379 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1381 if (!reg)
1387 mask = reg;
1392 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1395 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1398 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1399 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1400 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1416 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1417 reg |= mask;
1418 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1433 u32 reg;
1437 reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
1442 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1469 u32 reg;
1482 reg = rt2x00mmio_register_read(rt2x00dev, CSR0);
1484 rt2x00_get_field32(reg, CSR0_REVISION));
1610 u32 reg;
1627 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
1628 rt2x00_set_field32(®, GPIOCSR_DIR0, 1);
1629 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1687 u32 reg;
1689 reg = rt2x00mmio_register_read(rt2x00dev, CSR17);
1690 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1691 reg = rt2x00mmio_register_read(rt2x00dev, CSR16);
1692 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1700 u32 reg;
1702 reg = rt2x00mmio_register_read(rt2x00dev, CSR15);
1703 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);