Lines Matching refs:dev
16 static void mt7601u_agc_reset(struct mt7601u_dev *dev);
19 mt7601u_rf_wr(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 value)
23 if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) ||
26 if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
29 mutex_lock(&dev->reg_atomic_mutex);
31 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) {
36 mt7601u_wr(dev, MT_RF_CSR_CFG,
42 trace_rf_write(dev, bank, offset, value);
44 mutex_unlock(&dev->reg_atomic_mutex);
47 dev_err(dev->dev, "Error: RF write %02hhx:%02hhx failed:%d!!\n",
54 mt7601u_rf_rr(struct mt7601u_dev *dev, u8 bank, u8 offset)
59 if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) ||
62 if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
65 mutex_lock(&dev->reg_atomic_mutex);
67 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))
70 mt7601u_wr(dev, MT_RF_CSR_CFG,
75 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))
78 val = mt7601u_rr(dev, MT_RF_CSR_CFG);
82 trace_rf_read(dev, bank, offset, ret);
85 mutex_unlock(&dev->reg_atomic_mutex);
88 dev_err(dev->dev, "Error: RF read %02hhx:%02hhx failed:%d!!\n",
95 mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val)
99 ret = mt7601u_rf_rr(dev, bank, offset);
103 ret = mt7601u_rf_wr(dev, bank, offset, val);
111 mt7601u_rf_set(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 val)
113 return mt7601u_rf_rmw(dev, bank, offset, 0, val);
117 mt7601u_rf_clear(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask)
119 return mt7601u_rf_rmw(dev, bank, offset, mask, 0);
122 static void mt7601u_bbp_wr(struct mt7601u_dev *dev, u8 offset, u8 val)
124 if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) ||
125 test_bit(MT7601U_STATE_REMOVED, &dev->state))
128 mutex_lock(&dev->reg_atomic_mutex);
130 if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) {
131 dev_err(dev->dev, "Error: BBP write %02hhx failed!!\n", offset);
135 mt7601u_wr(dev, MT_BBP_CSR_CFG,
139 trace_bbp_write(dev, offset, val);
141 mutex_unlock(&dev->reg_atomic_mutex);
144 static int mt7601u_bbp_rr(struct mt7601u_dev *dev, u8 offset)
149 if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)))
151 if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
154 mutex_lock(&dev->reg_atomic_mutex);
156 if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000))
159 mt7601u_wr(dev, MT_BBP_CSR_CFG,
164 if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000))
167 val = mt7601u_rr(dev, MT_BBP_CSR_CFG);
170 trace_bbp_read(dev, offset, ret);
173 mutex_unlock(&dev->reg_atomic_mutex);
176 dev_err(dev->dev, "Error: BBP read %02hhx failed:%d!!\n",
182 static int mt7601u_bbp_rmw(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val)
186 ret = mt7601u_bbp_rr(dev, offset);
190 mt7601u_bbp_wr(dev, offset, val);
195 static u8 mt7601u_bbp_rmc(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val)
199 ret = mt7601u_bbp_rr(dev, offset);
204 mt7601u_bbp_wr(dev, offset, val);
209 int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev)
215 val = mt7601u_bbp_rr(dev, MT_BBP_REG_VERSION);
221 dev_err(dev->dev, "Error: BBP is not ready\n");
228 u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below)
230 return mt7601u_bbp_rmc(dev, 3, 0x20, below ? 0x20 : 0);
233 int mt7601u_phy_get_rssi(struct mt7601u_dev *dev,
257 val -= dev->ee->lna_gain;
258 val -= dev->ee->rssi_offset[0];
263 static void mt7601u_vco_cal(struct mt7601u_dev *dev)
265 mt7601u_rf_wr(dev, 0, 4, 0x0a);
266 mt7601u_rf_wr(dev, 0, 5, 0x20);
267 mt7601u_rf_set(dev, 0, 4, BIT(7));
271 static int mt7601u_set_bw_filter(struct mt7601u_dev *dev, bool cal)
278 if (dev->bw != MT_BW_20)
282 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter | 1);
286 return mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter);
289 static int mt7601u_load_bbp_temp_table_bw(struct mt7601u_dev *dev)
293 if (WARN_ON(dev->temp_mode > MT_TEMP_MODE_LOW))
296 t = &bbp_mode_table[dev->temp_mode][dev->bw];
298 return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, t->regs, t->n);
301 static int mt7601u_bbp_temp(struct mt7601u_dev *dev, int mode, const char *name)
306 if (dev->temp_mode == mode)
309 dev->temp_mode = mode;
310 trace_temp_mode(dev, mode);
312 t = bbp_mode_table[dev->temp_mode];
313 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,
318 return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,
319 t[dev->bw].regs, t[dev->bw].n);
322 static void mt7601u_apply_ch14_fixup(struct mt7601u_dev *dev, int hw_chan)
324 struct mt7601u_rate_power *t = &dev->ee->power_rate_table;
326 if (hw_chan != 14 || dev->bw != MT_BW_20) {
327 mt7601u_bbp_rmw(dev, 4, 0x20, 0);
328 mt7601u_bbp_wr(dev, 178, 0xff);
330 t->cck[0].bw20 = dev->ee->real_cck_bw20[0];
331 t->cck[1].bw20 = dev->ee->real_cck_bw20[1];
333 mt7601u_bbp_wr(dev, 4, 0x60);
334 mt7601u_bbp_wr(dev, 178, 0);
337 t->cck[0].bw20 = dev->ee->real_cck_bw20[0] - 2;
338 t->cck[1].bw20 = dev->ee->real_cck_bw20[1] - 2;
342 static int __mt7601u_phy_set_channel(struct mt7601u_dev *dev,
366 { 62, 0x37 - dev->ee->lna_gain },
367 { 63, 0x37 - dev->ee->lna_gain },
368 { 64, 0x37 - dev->ee->lna_gain },
374 struct mt7601u_rate_power *t = &dev->ee->power_rate_table;
392 dev_err(dev->dev, "Error: invalid 40MHz channel!!\n");
395 if (bw != dev->bw || chan_ext_below != dev->chan_ext_below) {
396 dev_dbg(dev->dev, "Info: switching HT mode bw:%d below:%d\n",
399 mt7601u_bbp_set_bw(dev, bw);
401 mt7601u_bbp_set_ctrlch(dev, chan_ext_below);
402 mt7601u_mac_set_ctrlch(dev, chan_ext_below);
403 dev->chan_ext_below = chan_ext_below;
409 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_RF,
414 mt7601u_rmw(dev, MT_TX_ALC_CFG_0, 0x3f3f,
415 dev->ee->chan_pwr[chan_idx] & 0x3f);
417 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,
422 mt7601u_vco_cal(dev);
423 mt7601u_bbp_set_bw(dev, bw);
424 ret = mt7601u_set_bw_filter(dev, false);
428 mt7601u_apply_ch14_fixup(dev, chan->hw_value);
429 mt7601u_wr(dev, MT_TX_PWR_CFG_0, int_to_s6(t->ofdm[1].bw20) << 24 |
434 if (test_bit(MT7601U_STATE_SCANNING, &dev->state))
435 mt7601u_agc_reset(dev);
437 dev->chandef = *chandef;
442 int mt7601u_phy_set_channel(struct mt7601u_dev *dev,
447 cancel_delayed_work_sync(&dev->cal_work);
448 cancel_delayed_work_sync(&dev->freq_cal.work);
450 mutex_lock(&dev->hw_atomic_mutex);
451 ret = __mt7601u_phy_set_channel(dev, chandef);
452 mutex_unlock(&dev->hw_atomic_mutex);
456 if (test_bit(MT7601U_STATE_SCANNING, &dev->state))
459 ieee80211_queue_delayed_work(dev->hw, &dev->cal_work,
461 if (dev->freq_cal.enabled)
462 ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work,
474 * @dev: pointer to adapter structure
484 static u8 mt7601u_bbp_r47_get(struct mt7601u_dev *dev, u8 reg, u8 flag)
487 mt7601u_bbp_wr(dev, 47, flag);
489 return mt7601u_bbp_rr(dev, 49);
492 static s8 mt7601u_read_bootup_temp(struct mt7601u_dev *dev)
498 rf_set = mt7601u_rr(dev, MT_RF_SETTING_0);
499 rf_bp = mt7601u_rr(dev, MT_RF_BYPASS_0);
501 mt7601u_wr(dev, MT_RF_BYPASS_0, 0);
502 mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000010);
503 mt7601u_wr(dev, MT_RF_BYPASS_0, 0x00000010);
505 bbp_val = mt7601u_bbp_rmw(dev, 47, 0, 0x10);
507 mt7601u_bbp_wr(dev, 22, 0x40);
510 bbp_val = mt7601u_bbp_rr(dev, 47);
512 temp = mt7601u_bbp_r47_get(dev, bbp_val, BBP_R47_F_TEMP);
514 mt7601u_bbp_wr(dev, 22, 0);
516 bbp_val = mt7601u_bbp_rr(dev, 21);
518 mt7601u_bbp_wr(dev, 21, bbp_val);
520 mt7601u_bbp_wr(dev, 21, bbp_val);
522 mt7601u_wr(dev, MT_RF_BYPASS_0, 0);
523 mt7601u_wr(dev, MT_RF_SETTING_0, rf_set);
524 mt7601u_wr(dev, MT_RF_BYPASS_0, rf_bp);
526 trace_read_temp(dev, temp);
530 static s8 mt7601u_read_temp(struct mt7601u_dev *dev)
536 val = mt7601u_bbp_rmw(dev, 47, 0x7f, 0x10);
540 val = mt7601u_bbp_rr(dev, 47);
542 temp = mt7601u_bbp_r47_get(dev, val, BBP_R47_F_TEMP);
544 trace_read_temp(dev, temp);
548 static void mt7601u_rxdc_cal(struct mt7601u_dev *dev)
559 mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL);
560 mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX);
562 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,
565 dev_err(dev->dev, "%s intro failed:%d\n", __func__, ret);
570 mt7601u_bbp_wr(dev, 158, 0x8c);
571 if (mt7601u_bbp_rr(dev, 159) == 0x0c)
575 dev_err(dev->dev, "%s timed out\n", __func__);
577 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);
579 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,
582 dev_err(dev->dev, "%s outro failed:%d\n", __func__, ret);
584 mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);
587 void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev)
589 mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->curr_temp);
591 mt7601u_rxdc_cal(dev);
627 mt7601u_set_initial_tssi(struct mt7601u_dev *dev, s16 tssi_db, s16 tssi_hvga_db)
629 struct tssi_data *d = &dev->ee->tssi_data;
634 mt76_rmw(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
638 static void mt7601u_tssi_dc_gain_cal(struct mt7601u_dev *dev)
645 mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000030);
646 mt7601u_wr(dev, MT_RF_BYPASS_0, 0x000c0030);
647 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);
649 mt7601u_bbp_wr(dev, 58, 0);
650 mt7601u_bbp_wr(dev, 241, 0x2);
651 mt7601u_bbp_wr(dev, 23, 0x8);
652 bbp_r47 = mt7601u_bbp_rr(dev, 47);
655 rf_vga = mt7601u_rf_rr(dev, 5, 3);
656 mt7601u_rf_wr(dev, 5, 3, 8);
659 rf_mixer = mt7601u_rf_rr(dev, 4, 39);
660 mt7601u_rf_wr(dev, 4, 39, 0);
663 mt7601u_rf_wr(dev, 4, 39, (i & 1) ? rf_mixer : 0);
665 mt7601u_bbp_wr(dev, 23, (i < 2) ? 0x08 : 0x02);
666 mt7601u_rf_wr(dev, 5, 3, (i < 2) ? 0x08 : 0x11);
669 mt7601u_bbp_wr(dev, 22, 0);
670 mt7601u_bbp_wr(dev, 244, 0);
672 mt7601u_bbp_wr(dev, 21, 1);
674 mt7601u_bbp_wr(dev, 21, 0);
677 mt7601u_bbp_wr(dev, 47, 0x50);
678 mt7601u_bbp_wr(dev, (i & 1) ? 244 : 22, (i & 1) ? 0x31 : 0x40);
681 if (!(mt7601u_bbp_rr(dev, 47) & 0x10))
684 dev_err(dev->dev, "%s timed out\n", __func__);
687 mt7601u_bbp_wr(dev, 47, 0x40);
688 res[i] = mt7601u_bbp_rr(dev, 49);
693 dev->tssi_init = res[0];
694 dev->tssi_init_hvga = res[2];
695 dev->tssi_init_hvga_offset_db = tssi_init_hvga_db - tssi_init_db;
697 dev_dbg(dev->dev,
699 dev->tssi_init, tssi_init_db, dev->tssi_init_hvga,
700 tssi_init_hvga_db, dev->tssi_init_hvga_offset_db);
702 mt7601u_bbp_wr(dev, 22, 0);
703 mt7601u_bbp_wr(dev, 244, 0);
705 mt7601u_bbp_wr(dev, 21, 1);
707 mt7601u_bbp_wr(dev, 21, 0);
709 mt7601u_wr(dev, MT_RF_BYPASS_0, 0);
710 mt7601u_wr(dev, MT_RF_SETTING_0, 0);
712 mt7601u_rf_wr(dev, 5, 3, rf_vga);
713 mt7601u_rf_wr(dev, 4, 39, rf_mixer);
714 mt7601u_bbp_wr(dev, 47, bbp_r47);
716 mt7601u_set_initial_tssi(dev, tssi_init_db, tssi_init_hvga_db);
719 static int mt7601u_temp_comp(struct mt7601u_dev *dev, bool on)
723 temp = (dev->raw_temp - dev->ee->ref_temp) * MT_EE_TEMPERATURE_SLOPE;
724 dev->curr_temp = temp;
727 if (temp - dev->dpd_temp > 450 || temp - dev->dpd_temp < -450) {
728 dev->dpd_temp = temp;
730 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp);
734 mt7601u_vco_cal(dev);
736 dev_dbg(dev->dev, "Recalibrate DPD\n");
740 if (temp < -50 && !dev->pll_lock_protect) { /* < 20C */
741 dev->pll_lock_protect = true;
743 mt7601u_rf_wr(dev, 4, 4, 6);
744 mt7601u_rf_clear(dev, 4, 10, 0x30);
746 dev_dbg(dev->dev, "PLL lock protect on - too cold\n");
747 } else if (temp > 50 && dev->pll_lock_protect) { /* > 30C */
748 dev->pll_lock_protect = false;
750 mt7601u_rf_wr(dev, 4, 4, 0);
751 mt7601u_rf_rmw(dev, 4, 10, 0x30, 0x10);
753 dev_dbg(dev->dev, "PLL lock protect off\n");
763 return mt7601u_bbp_temp(dev, MT_TEMP_MODE_HIGH, "high");
765 return mt7601u_bbp_temp(dev, MT_TEMP_MODE_NORMAL, "normal");
767 return mt7601u_bbp_temp(dev, MT_TEMP_MODE_LOW, "low");
771 static int mt7601u_current_tx_power(struct mt7601u_dev *dev)
773 return dev->ee->chan_pwr[dev->chandef.chan->hw_value - 1];
776 static bool mt7601u_use_hvga(struct mt7601u_dev *dev)
778 return !(mt7601u_current_tx_power(dev) > 20);
782 mt7601u_phy_rf_pa_mode_val(struct mt7601u_dev *dev, int phy_mode, int tx_rate)
792 reg = dev->rf_pa_mode[0];
795 reg = dev->rf_pa_mode[1];
803 mt7601u_tssi_params_get(struct mt7601u_dev *dev)
811 bbp_r47 = mt7601u_bbp_rr(dev, 47);
813 p.tssi0 = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TSSI);
814 dev->raw_temp = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TEMP);
815 pkt_type = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_PKT_T);
817 p.trgt_power = mt7601u_current_tx_power(dev);
822 rate_table = dev->ee->power_rate_table.cck;
827 rate_table = dev->ee->power_rate_table.ofdm;
831 tx_rate = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TX_RATE);
833 rate_table = dev->ee->power_rate_table.ht;
837 if (dev->bw == MT_BW_20)
844 dev_dbg(dev->dev, "tx_rate:%02hhx pwr:%08x\n", tx_rate, p.trgt_power);
846 p.trgt_power += mt7601u_phy_rf_pa_mode_val(dev, pkt_type & 0x03,
851 if (mt7601u_bbp_rr(dev, 4) & 0x20)
852 p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 18022 : 9830;
854 p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 819 : 24576;
857 p.trgt_power += static_power[mt7601u_bbp_rr(dev, 1) & 0x03];
859 p.trgt_power += dev->ee->tssi_data.tx0_delta_offset;
861 dev_dbg(dev->dev,
863 p.tssi0, p.trgt_power, dev->raw_temp, pkt_type);
868 static bool mt7601u_tssi_read_ready(struct mt7601u_dev *dev)
870 return !(mt7601u_bbp_rr(dev, 47) & 0x10);
873 static int mt7601u_tssi_cal(struct mt7601u_dev *dev)
883 if (!dev->ee->tssi_enabled)
886 hvga = mt7601u_use_hvga(dev);
887 if (!dev->tssi_read_trig)
888 return mt7601u_mcu_tssi_read_kick(dev, hvga);
890 if (!mt7601u_tssi_read_ready(dev))
893 params = mt7601u_tssi_params_get(dev);
895 tssi_init = (hvga ? dev->tssi_init_hvga : dev->tssi_init);
898 dev_dbg(dev->dev, "tssi dc:%04hx db:%04hx hvga:%d\n",
901 if (dev->chandef.chan->hw_value < 5)
902 tssi_offset = dev->ee->tssi_data.offset[0];
903 else if (dev->chandef.chan->hw_value < 9)
904 tssi_offset = dev->ee->tssi_data.offset[1];
906 tssi_offset = dev->ee->tssi_data.offset[2];
909 tssi_db -= dev->tssi_init_hvga_offset_db;
911 curr_pwr = tssi_db * dev->ee->tssi_data.slope + (tssi_offset << 9);
913 dev_dbg(dev->dev, "Power curr:%08x diff:%08x\n", curr_pwr, diff_pwr);
916 dev_err(dev->dev, "Error: TSSI upper saturation\n");
920 dev_err(dev->dev, "Error: TSSI lower saturation\n");
924 if ((dev->prev_pwr_diff ^ diff_pwr) < 0 && abs(diff_pwr) < 4096 &&
925 (abs(diff_pwr) > abs(dev->prev_pwr_diff) ||
926 (diff_pwr > 0 && diff_pwr == -dev->prev_pwr_diff)))
929 dev->prev_pwr_diff = diff_pwr;
934 dev_dbg(dev->dev, "final diff: %08x\n", diff_pwr);
936 val = mt7601u_rr(dev, MT_TX_ALC_CFG_1);
940 mt7601u_wr(dev, MT_TX_ALC_CFG_1, val);
942 return mt7601u_mcu_tssi_read_kick(dev, hvga);
945 static u8 mt7601u_agc_default(struct mt7601u_dev *dev)
947 return (dev->ee->lna_gain - 8) * 2 + 0x34;
950 static void mt7601u_agc_reset(struct mt7601u_dev *dev)
952 u8 agc = mt7601u_agc_default(dev);
954 mt7601u_bbp_wr(dev, 66, agc);
957 void mt7601u_agc_save(struct mt7601u_dev *dev)
959 dev->agc_save = mt7601u_bbp_rr(dev, 66);
962 void mt7601u_agc_restore(struct mt7601u_dev *dev)
964 mt7601u_bbp_wr(dev, 66, dev->agc_save);
967 static void mt7601u_agc_tune(struct mt7601u_dev *dev)
969 u8 val = mt7601u_agc_default(dev);
972 if (test_bit(MT7601U_STATE_SCANNING, &dev->state))
979 spin_lock_bh(&dev->con_mon_lock);
980 avg_rssi = ewma_rssi_read(&dev->avg_rssi);
981 spin_unlock_bh(&dev->con_mon_lock);
991 if (val != mt7601u_bbp_rr(dev, 66))
992 mt7601u_bbp_wr(dev, 66, val);
1001 struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,
1004 mt7601u_agc_tune(dev);
1005 mt7601u_tssi_cal(dev);
1007 if (!dev->ee->tssi_enabled)
1008 dev->raw_temp = mt7601u_read_temp(dev);
1009 mt7601u_temp_comp(dev, true); /* TODO: find right value for @on */
1011 ieee80211_queue_delayed_work(dev->hw, &dev->cal_work,
1016 __mt7601u_phy_freq_cal(struct mt7601u_dev *dev, s8 last_offset, u8 phy_mode)
1020 trace_freq_cal_offset(dev, phy_mode, last_offset);
1046 dev->freq_cal.adjusting = true;
1048 dev->freq_cal.adjusting = false;
1050 if (!dev->freq_cal.adjusting)
1054 if (dev->freq_cal.freq > 0)
1055 dev->freq_cal.freq--;
1057 dev->freq_cal.adjusting = false;
1059 if (dev->freq_cal.freq < 0xbf)
1060 dev->freq_cal.freq++;
1062 dev->freq_cal.adjusting = false;
1065 trace_freq_cal_adjust(dev, dev->freq_cal.freq);
1066 mt7601u_rf_wr(dev, 0, 12, dev->freq_cal.freq);
1067 mt7601u_vco_cal(dev);
1069 return dev->freq_cal.adjusting ? MT_FREQ_CAL_ADJ_INTERVAL :
1075 struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,
1081 spin_lock_bh(&dev->con_mon_lock);
1082 last_offset = dev->bcn_freq_off;
1083 phy_mode = dev->bcn_phy_mode;
1084 spin_unlock_bh(&dev->con_mon_lock);
1086 delay = __mt7601u_phy_freq_cal(dev, last_offset, phy_mode);
1087 ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, delay);
1089 spin_lock_bh(&dev->con_mon_lock);
1090 dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID;
1091 spin_unlock_bh(&dev->con_mon_lock);
1094 void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev,
1098 cancel_delayed_work_sync(&dev->freq_cal.work);
1101 spin_lock_bh(&dev->con_mon_lock);
1102 ether_addr_copy(dev->ap_bssid, info->bssid);
1103 ewma_rssi_init(&dev->avg_rssi);
1104 dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID;
1105 spin_unlock_bh(&dev->con_mon_lock);
1107 dev->freq_cal.freq = dev->ee->rf_freq_off;
1108 dev->freq_cal.enabled = info->assoc;
1109 dev->freq_cal.adjusting = false;
1112 ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work,
1116 static int mt7601u_init_cal(struct mt7601u_dev *dev)
1121 dev->raw_temp = mt7601u_read_bootup_temp(dev);
1122 dev->curr_temp = (dev->raw_temp - dev->ee->ref_temp) *
1124 dev->dpd_temp = dev->curr_temp;
1126 mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL);
1128 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_R, 0);
1132 ret = mt7601u_rf_rr(dev, 0, 4);
1136 ret = mt7601u_rf_wr(dev, 0, 4, ret);
1141 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXDCOC, 0);
1145 mt7601u_rxdc_cal(dev);
1147 ret = mt7601u_set_bw_filter(dev, true);
1150 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_LOFT, 0);
1153 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXIQ, 0);
1156 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_RXIQ, 0);
1159 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp);
1163 mt7601u_rxdc_cal(dev);
1165 mt7601u_tssi_dc_gain_cal(dev);
1167 mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);
1169 mt7601u_temp_comp(dev, true);
1174 int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw)
1178 if (bw == dev->bw) {
1180 mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10);
1184 dev->bw = bw;
1187 old = mt7601u_rr(dev, MT_MAC_SYS_CTRL);
1189 mt7601u_wr(dev, MT_MAC_SYS_CTRL, val);
1190 mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX | MT_MAC_STATUS_RX,
1193 mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10);
1195 mt7601u_wr(dev, MT_MAC_SYS_CTRL, old);
1197 return mt7601u_load_bbp_temp_table_bw(dev);
1202 * @dev: pointer to adapter structure
1205 void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path)
1207 mt7601u_bbp_rmw(dev, 3, 0x18, path << 3);
1212 * @dev: pointer to adapter structure
1215 void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 dac)
1217 mt7601u_bbp_rmc(dev, 1, 0x18, dac << 3);
1220 int mt7601u_phy_init(struct mt7601u_dev *dev)
1224 dev->rf_pa_mode[0] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG0);
1225 dev->rf_pa_mode[1] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG1);
1227 ret = mt7601u_rf_wr(dev, 0, 12, dev->ee->rf_freq_off);
1230 ret = mt7601u_write_reg_pairs(dev, 0, rf_central,
1234 ret = mt7601u_write_reg_pairs(dev, 0, rf_channel,
1238 ret = mt7601u_write_reg_pairs(dev, 0, rf_vga, ARRAY_SIZE(rf_vga));
1242 ret = mt7601u_init_cal(dev);
1246 dev->prev_pwr_diff = 100;
1248 INIT_DELAYED_WORK(&dev->cal_work, mt7601u_phy_calibrate);
1249 INIT_DELAYED_WORK(&dev->freq_cal.work, mt7601u_phy_freq_cal);