Lines Matching defs:msg
393 mt76_testmode_dump_stats(struct mt76_dev *dev, struct sk_buff *msg)
405 if (nla_put_u32(msg, MT76_TM_STATS_ATTR_TX_PENDING, td->tx_pending) ||
406 nla_put_u32(msg, MT76_TM_STATS_ATTR_TX_QUEUED, td->tx_queued) ||
407 nla_put_u32(msg, MT76_TM_STATS_ATTR_TX_DONE, td->tx_done) ||
408 nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_PACKETS, rx_packets,
410 nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_FCS_ERROR, rx_fcs_error,
415 return dev->test_ops->dump_stats(dev, msg);
420 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg,
449 a = nla_nest_start(msg, MT76_TM_ATTR_STATS);
451 err = mt76_testmode_dump_stats(dev, msg);
452 nla_nest_end(msg, a);
461 if (nla_put_u32(msg, MT76_TM_ATTR_STATE, td->state))
465 (nla_put_string(msg, MT76_TM_ATTR_MTD_PART, td->mtd_name) ||
466 nla_put_u32(msg, MT76_TM_ATTR_MTD_OFFSET, td->mtd_offset)))
469 if (nla_put_u32(msg, MT76_TM_ATTR_TX_COUNT, td->tx_count) ||
470 nla_put_u32(msg, MT76_TM_ATTR_TX_LENGTH, td->tx_msdu_len) ||
471 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_MODE, td->tx_rate_mode) ||
472 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_NSS, td->tx_rate_nss) ||
473 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_IDX, td->tx_rate_idx) ||
474 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_SGI, td->tx_rate_sgi) ||
475 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_LDPC, td->tx_rate_ldpc) ||
477 nla_put_u8(msg, MT76_TM_ATTR_TX_ANTENNA, td->tx_antenna_mask)) ||
479 nla_put_u8(msg, MT76_TM_ATTR_TX_POWER_CONTROL, td->tx_power_control)) ||
481 nla_put_u8(msg, MT76_TM_ATTR_FREQ_OFFSET, td->freq_offset)))
485 a = nla_nest_start(msg, MT76_TM_ATTR_TX_POWER);
490 if (nla_put_u8(msg, i, td->tx_power[i]))
493 nla_nest_end(msg, a);