Lines Matching refs:port
262 struct usb_tx_data_port *port;
279 port = &card->port[i];
280 if (context->ep == port->tx_data_ep) {
281 atomic_dec(&port->tx_data_urb_pending);
282 port->block_status = false;
359 struct usb_tx_data_port *port;
379 port = &card->port[i];
381 usb_kill_urb(port->tx_data_list[j].urb);
382 usb_free_urb(port->tx_data_list[j].urb);
383 port->tx_data_list[j].urb = NULL;
477 card->port[0].tx_data_ep = usb_endpoint_num(epd);
478 atomic_set(&card->port[0].tx_data_urb_pending, 0);
487 card->port[1].tx_data_ep = usb_endpoint_num(epd);
488 atomic_set(&card->port[1].tx_data_urb_pending, 0);
551 struct usb_tx_data_port *port;
594 port = &card->port[i];
596 if (port->tx_data_list[j].urb)
597 usb_kill_urb(port->tx_data_list[j].urb);
769 card->port[i].block_status = false;
789 if (active_port == card->port[i].tx_data_ep)
790 card->port[i].block_status = false;
792 card->port[i].block_status = true;
803 if (priv->usb_port == card->port[idx].tx_data_ep)
804 return !card->port[idx].block_status;
816 if (!card->port[i].block_status)
823 struct usb_tx_data_port *port, u8 ep,
853 atomic_inc(&port->tx_data_urb_pending);
856 atomic_read(&port->tx_data_urb_pending) ==
858 port->block_status = true;
869 atomic_dec(&port->tx_data_urb_pending);
870 port->block_status = false;
872 if (port->tx_data_ix)
873 port->tx_data_ix--;
875 port->tx_data_ix = MWIFIEX_TX_DATA_URB;
884 struct usb_tx_data_port *port,
896 if (port->tx_aggr.timer_cnxt.is_hold_timer_set) {
897 del_timer(&port->tx_aggr.timer_cnxt.hold_timer);
898 port->tx_aggr.timer_cnxt.is_hold_timer_set = false;
899 port->tx_aggr.timer_cnxt.hold_tmo_msecs = 0;
902 skb_aggr = mwifiex_alloc_dma_align_buf(port->tx_aggr.aggr_len,
908 while ((skb_tmp = skb_dequeue(&port->tx_aggr.aggr_list)))
911 port->tx_aggr.aggr_num = 0;
912 port->tx_aggr.aggr_len = 0;
919 while ((skb_tmp = skb_dequeue(&port->tx_aggr.aggr_list))) {
924 if (skb_queue_empty(&port->tx_aggr.aggr_list)) {
943 port->tx_aggr.aggr_num--;
944 port->tx_aggr.aggr_len -= (skb_tmp->len + pad);
952 port->tx_aggr.aggr_num = 0;
953 port->tx_aggr.aggr_len = 0;
971 struct usb_tx_data_port *port)
991 if (port->tx_aggr.aggr_len + skb->len + pad >
999 if (port->tx_aggr.aggr_len + skb->len + pad +
1002 port->tx_aggr.aggr_num + 2 >
1012 if (port->tx_aggr.aggr_num > 0) {
1014 if (port->tx_aggr.aggr_len + skb->len + pad >
1037 if (skb_queue_empty(&port->tx_aggr.aggr_list)) {
1051 skb_queue_tail(&port->tx_aggr.aggr_list, skb);
1052 port->tx_aggr.aggr_len += (skb->len + pad);
1053 port->tx_aggr.aggr_num++;
1062 if (!port->tx_aggr.timer_cnxt.is_hold_timer_set) {
1063 port->tx_aggr.timer_cnxt.hold_tmo_msecs =
1066 port->tx_aggr.timer_cnxt.hold_tmo_msecs;
1067 mod_timer(&port->tx_aggr.timer_cnxt.hold_timer,
1069 port->tx_aggr.timer_cnxt.is_hold_timer_set = true;
1071 if (port->tx_aggr.timer_cnxt.hold_tmo_msecs <
1075 ++port->tx_aggr.timer_cnxt.hold_tmo_msecs;
1076 mod_timer(&port->tx_aggr.timer_cnxt.hold_timer,
1084 ret = mwifiex_usb_prepare_tx_aggr_skb(adapter, port, &skb_send);
1086 context = &port->tx_data_list[port->tx_data_ix++];
1087 ret = mwifiex_usb_construct_send_urb(adapter, port, ep,
1097 if (atomic_read(&port->tx_data_urb_pending) >=
1099 port->block_status = true;
1107 if (port->tx_data_ix >= MWIFIEX_TX_DATA_URB)
1108 port->tx_data_ix = 0;
1116 context = &port->tx_data_list[port->tx_data_ix++];
1117 return mwifiex_usb_construct_send_urb(adapter, port, ep,
1123 skb_queue_tail(&port->tx_aggr.aggr_list, skb);
1124 port->tx_aggr.aggr_len += (skb->len + pad);
1125 port->tx_aggr.aggr_num++;
1127 if (!port->tx_aggr.timer_cnxt.is_hold_timer_set) {
1128 port->tx_aggr.timer_cnxt.hold_tmo_msecs =
1130 timeout = port->tx_aggr.timer_cnxt.hold_tmo_msecs;
1131 mod_timer(&port->tx_aggr.timer_cnxt.hold_timer,
1133 port->tx_aggr.timer_cnxt.is_hold_timer_set = true;
1147 struct usb_tx_data_port *port = timer_context->port;
1150 spin_lock_bh(&port->tx_aggr_lock);
1151 err = mwifiex_usb_prepare_tx_aggr_skb(adapter, port, &skb_send);
1158 if (atomic_read(&port->tx_data_urb_pending) >=
1160 port->block_status = true;
1167 if (port->tx_data_ix >= MWIFIEX_TX_DATA_URB)
1168 port->tx_data_ix = 0;
1170 urb_cnxt = &port->tx_data_list[port->tx_data_ix++];
1171 err = mwifiex_usb_construct_send_urb(adapter, port, port->tx_data_ep,
1177 spin_unlock_bh(&port->tx_aggr_lock);
1187 struct usb_tx_data_port *port = NULL;
1206 /* get the data port structure for endpoint */
1208 if (ep == card->port[idx].tx_data_ep) {
1209 port = &card->port[idx];
1210 if (atomic_read(&port->tx_data_urb_pending)
1212 port->block_status = true;
1217 if (port->tx_data_ix >= MWIFIEX_TX_DATA_URB)
1218 port->tx_data_ix = 0;
1223 if (!port) {
1224 mwifiex_dbg(adapter, ERROR, "Wrong usb tx data port\n");
1229 spin_lock_bh(&port->tx_aggr_lock);
1231 tx_param, port);
1232 spin_unlock_bh(&port->tx_aggr_lock);
1236 context = &port->tx_data_list[port->tx_data_ix++];
1239 return mwifiex_usb_construct_send_urb(adapter, port, ep, context, skb);
1245 struct usb_tx_data_port *port;
1256 port = &card->port[i];
1257 if (!port->tx_data_ep)
1259 port->tx_data_ix = 0;
1260 skb_queue_head_init(&port->tx_aggr.aggr_list);
1261 if (port->tx_data_ep == MWIFIEX_USB_EP_DATA)
1262 port->block_status = false;
1264 port->block_status = true;
1266 port->tx_data_list[j].adapter = adapter;
1267 port->tx_data_list[j].ep = port->tx_data_ep;
1268 port->tx_data_list[j].urb =
1270 if (!port->tx_data_list[j].urb)
1274 port->tx_aggr.timer_cnxt.adapter = adapter;
1275 port->tx_aggr.timer_cnxt.port = port;
1276 port->tx_aggr.timer_cnxt.is_hold_timer_set = false;
1277 port->tx_aggr.timer_cnxt.hold_tmo_msecs = 0;
1278 timer_setup(&port->tx_aggr.timer_cnxt.hold_timer,
1362 struct usb_tx_data_port *port;
1367 port = &card->port[idx];
1370 skb_dequeue(&port->tx_aggr.aggr_list)))
1373 if (port->tx_aggr.timer_cnxt.hold_timer.function)
1374 del_timer_sync(&port->tx_aggr.timer_cnxt.hold_timer);
1375 port->tx_aggr.timer_cnxt.is_hold_timer_set = false;
1376 port->tx_aggr.timer_cnxt.hold_tmo_msecs = 0;