Lines Matching defs:trans
94 static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
101 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
105 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
110 IWL_DEBUG_EEPROM(trans->dev,
120 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
122 iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
126 static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)
128 u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
130 IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp);
135 IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n",
143 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp);
149 IWL_ERR(trans,
162 static void iwl_set_otp_access_absolute(struct iwl_trans *trans)
164 iwl_read32(trans, CSR_OTP_GP_REG);
166 iwl_clear_bit(trans, CSR_OTP_GP_REG,
170 static int iwl_nvm_is_otp(struct iwl_trans *trans)
175 switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) {
177 IWL_ERR(trans, "Unknown hardware type\n");
185 otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
192 static int iwl_init_otp_access(struct iwl_trans *trans)
196 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
200 iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
203 iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
210 if (trans->trans_cfg->base_params->shadow_ram_support)
211 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
217 static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
224 iwl_write32(trans, CSR_EEPROM_REG,
226 ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
231 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
234 r = iwl_read32(trans, CSR_EEPROM_REG);
236 otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
240 iwl_set_bit(trans, CSR_OTP_GP_REG,
242 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");
248 iwl_set_bit(trans, CSR_OTP_GP_REG,
250 IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");
259 static bool iwl_is_otp_empty(struct iwl_trans *trans)
266 if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) {
268 IWL_ERR(trans, "OTP is empty\n");
272 IWL_ERR(trans, "Unable to read first block of OTP list.\n");
289 static int iwl_find_otp_image(struct iwl_trans *trans,
297 iwl_set_otp_access_absolute(trans);
300 if (iwl_is_otp_empty(trans))
314 IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n",
316 if (iwl_read_otp_word(trans, next_link_addr, &link_value))
331 } while (usedblocks <= trans->trans_cfg->base_params->max_ll_items);
334 IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n");
346 int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
349 u32 gp = iwl_read32(trans, CSR_EEPROM_GP);
360 nvm_is_otp = iwl_nvm_is_otp(trans);
364 sz = trans->trans_cfg->base_params->eeprom_size;
365 IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz);
371 ret = iwl_eeprom_verify_signature(trans, nvm_is_otp);
373 IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
378 ret = iwl_eeprom_acquire_semaphore(trans);
380 IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n");
385 ret = iwl_init_otp_access(trans);
387 IWL_ERR(trans, "Failed to initialize OTP access.\n");
391 iwl_write32(trans, CSR_EEPROM_GP,
392 iwl_read32(trans, CSR_EEPROM_GP) &
395 iwl_set_bit(trans, CSR_OTP_GP_REG,
399 if (!trans->trans_cfg->base_params->shadow_ram_support) {
400 ret = iwl_find_otp_image(trans, &validblockaddr);
408 ret = iwl_read_otp_word(trans, addr, &eeprom_data);
419 iwl_write32(trans, CSR_EEPROM_REG,
422 ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
427 IWL_ERR(trans,
431 r = iwl_read32(trans, CSR_EEPROM_REG);
436 IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n",
439 iwl_eeprom_release_semaphore(trans);
446 iwl_eeprom_release_semaphore(trans);