Lines Matching defs:fwrt
102 * @fwrt: &struct iwl_fw_runtime
108 struct iwl_fw_runtime *fwrt;
519 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt,
536 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE,
542 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n",
558 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt,
570 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
571 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
579 if (!fw_has_capa(&fwrt->fw->ucode_capa,
599 IWL_DEBUG_FW(fwrt,
603 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i],
610 iwl_dbg_tlv_fragments_free(fwrt->trans,
624 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt,
631 if (!fw_has_capa(&fwrt->fw->ucode_capa,
639 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
643 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
657 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n",
684 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
694 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt)
699 ret = iwl_dbg_tlv_apply_buffer(fwrt, i);
701 IWL_WARN(fwrt,
707 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt,
722 iwl_trans_send_cmd(fwrt->trans, &cmd);
735 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data);
747 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt)
751 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
767 IWL_ERR(fwrt,
773 IWL_WARN(fwrt,
783 IWL_ERR(fwrt,
788 timer_node->fwrt = fwrt;
794 &fwrt->trans->dbg.periodic_trig_list);
796 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n");
829 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt,
845 IWL_DEBUG_FW(fwrt,
852 IWL_DEBUG_FW(fwrt,
865 IWL_WARN(fwrt,
883 IWL_DEBUG_FW(fwrt,
892 IWL_DEBUG_FW(fwrt,
898 IWL_DEBUG_FW(fwrt,
909 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt,
929 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n",
934 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match);
938 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt,
948 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv);
952 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt,
979 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt,
982 bool (*data_check)(struct iwl_fw_runtime *fwrt,
998 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data);
1005 data_check(fwrt, &dump_data, tp_data,
1007 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data);
1019 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
1021 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1027 IWL_DEBUG_FW(fwrt,
1029 fwrt->trans->dbg.domains_bitmap);
1031 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1033 &fwrt->trans->dbg.time_point[i];
1035 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
1041 &fwrt->trans->dbg.fw_mon_cfg[i];
1053 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i);
1055 IWL_WARN(fwrt,
1061 void iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt,
1067 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1072 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1073 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1077 iwl_dbg_tlv_init_cfg(fwrt);
1078 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL);
1081 iwl_dbg_tlv_apply_buffers(fwrt);
1082 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1083 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL);
1086 iwl_dbg_tlv_set_periodic_trigs(fwrt);
1087 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1092 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1093 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data,
1097 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1098 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL);