Lines Matching defs:il
31 il3945_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd)
41 return il_send_cmd(il, &cmd);
103 il3945_disable_events(struct il_priv *il)
159 base = le32_to_cpu(il->card_alive.log_event_table_ptr);
165 disable_ptr = il_read_targ_mem(il, base + (4 * sizeof(u32)));
166 array_size = il_read_targ_mem(il, base + (5 * sizeof(u32)));
172 il_write_targ_mem(il, disable_ptr + (i * sizeof(u32)),
238 il3945_rs_next_rate(struct il_priv *il, int rate)
242 switch (il->band) {
250 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
251 il_is_associated(il)) {
272 il3945_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
274 struct il_tx_queue *txq = &il->txq[txq_id];
284 ieee80211_tx_status_irqsafe(il->hw, skb);
286 il->ops->txq_free_tfd(il, txq);
290 txq_id != IL39_CMD_QUEUE_NUM && il->mac80211_registered)
291 il_wake_queue(il, txq);
298 il3945_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
304 struct il_tx_queue *txq = &il->txq[txq_id];
326 il->iw_mode == NL80211_IFTYPE_STATION) {
327 il_stop_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
355 il3945_tx_queue_reclaim(il, txq_id, idx);
370 il3945_accumulative_stats(struct il_priv *il, __le32 * stats)
377 prev_stats = (__le32 *) &il->_3945.stats;
378 accum_stats = (u32 *) &il->_3945.accum_stats;
379 delta = (u32 *) &il->_3945.delta_stats;
380 max_delta = (u32 *) &il->_3945.max_delta;
396 il->_3945.accum_stats.general.temperature =
397 il->_3945.stats.general.temperature;
398 il->_3945.accum_stats.general.ttl_timestamp =
399 il->_3945.stats.general.ttl_timestamp;
404 il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
412 il3945_accumulative_stats(il, (__le32 *) &pkt->u.raw);
415 memcpy(&il->_3945.stats, pkt->u.raw, sizeof(il->_3945.stats));
419 il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
426 memset(&il->_3945.accum_stats, 0,
428 memset(&il->_3945.delta_stats, 0,
430 memset(&il->_3945.max_delta, 0,
435 il3945_hdl_stats(il, rxb);
446 il3945_is_network_packet(struct il_priv *il, struct ieee80211_hdr *header)
450 switch (il->iw_mode) {
453 return ether_addr_equal_64bits(header->addr3, il->bssid);
456 return ether_addr_equal_64bits(header->addr2, il->bssid);
465 il3945_pass_packet_to_mac80211(struct il_priv *il, struct il_rx_buf *rxb,
475 u32 fraglen = PAGE_SIZE << il->hw_params.rx_page_order;
484 if (unlikely(!il->is_open)) {
489 if (unlikely(test_bit(IL_STOP_REASON_PASSIVE, &il->stop_reason))) {
490 il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
501 il_set_decrypted_flag(il, (struct ieee80211_hdr *)pkt,
513 il->alloc_rxb_page--;
516 il_update_stats(il, false, fc, len);
519 ieee80211_rx(il->hw, skb);
525 il3945_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
580 network_packet = il3945_is_network_packet(il, header);
587 il->_3945.last_beacon_time =
589 il->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
590 il->_3945.last_rx_rssi = rx_status.signal;
593 il3945_pass_packet_to_mac80211(il, rxb, &rx_status);
597 il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
636 il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
641 struct pci_dev *dev = il->pci_dev;
683 il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
687 u16 hw_value = ieee80211_get_tx_rate(il->hw, info)->hw_value;
730 il3945_sync_sta(struct il_priv *il, int sta_id, u16 tx_rate)
738 spin_lock_irqsave(&il->sta_lock, flags_spin);
739 station = &il->stations[sta_id];
744 il_send_add_sta(il, &station->sta, CMD_ASYNC);
745 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
752 il3945_set_pwr_vmain(struct il_priv *il)
758 if (pci_pme_capable(il->pci_dev, PCI_D3cold)) {
759 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
763 _il_poll_bit(il, CSR_GPIO_IN,
769 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
773 _il_poll_bit(il, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
778 il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
780 il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
781 il_wr(il, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
782 il_wr(il, FH39_RCSR_WPTR(0), 0);
783 il_wr(il, FH39_RCSR_CONFIG(0),
795 il_rd(il, FH39_RSSR_CTRL);
801 il3945_tx_reset(struct il_priv *il)
804 il_wr_prph(il, ALM_SCD_MODE_REG, 0x2);
807 il_wr_prph(il, ALM_SCD_ARASTAT_REG, 0x01);
810 il_wr_prph(il, ALM_SCD_TXFACT_REG, 0x3f);
812 il_wr_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
813 il_wr_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
814 il_wr_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);
815 il_wr_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);
817 il_wr(il, FH39_TSSR_CBB_BASE, il->_3945.shared_phys);
819 il_wr(il, FH39_TSSR_MSG_CONFIG,
837 il3945_txq_ctx_reset(struct il_priv *il)
841 il3945_hw_txq_ctx_free(il);
844 rc = il_alloc_txq_mem(il);
849 rc = il3945_tx_reset(il);
854 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
855 rc = il_tx_queue_init(il, txq_id);
865 il3945_hw_txq_ctx_free(il);
875 il3945_apm_init(struct il_priv *il)
877 int ret = il_apm_init(il);
880 il_wr_prph(il, APMG_RTC_INT_MSK_REG, 0x0);
881 il_wr_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
884 il_set_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
886 il_clear_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
892 il3945_nic_config(struct il_priv *il)
894 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
896 u8 rev_id = il->pci_dev->revision;
898 spin_lock_irqsave(&il->lock, flags);
907 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
911 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
917 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
924 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
928 il_clear_bit(il, CSR_HW_IF_CONFIG_REG,
933 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
940 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
943 spin_unlock_irqrestore(&il->lock, flags);
953 il3945_hw_nic_init(struct il_priv *il)
957 struct il_rx_queue *rxq = &il->rxq;
959 spin_lock_irqsave(&il->lock, flags);
960 il3945_apm_init(il);
961 spin_unlock_irqrestore(&il->lock, flags);
963 il3945_set_pwr_vmain(il);
964 il3945_nic_config(il);
968 rc = il_rx_queue_alloc(il);
974 il3945_rx_queue_reset(il, rxq);
976 il3945_rx_replenish(il);
978 il3945_rx_init(il, rxq);
982 il_rx_queue_update_write_ptr(il, rxq);
985 il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7);
987 rc = il3945_txq_ctx_reset(il);
991 set_bit(S_INIT, &il->status);
1002 il3945_hw_txq_ctx_free(struct il_priv *il)
1007 if (il->txq) {
1008 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1010 il_cmd_queue_free(il);
1012 il_tx_queue_free(il, txq_id);
1016 il_free_txq_mem(il);
1020 il3945_hw_txq_ctx_stop(struct il_priv *il)
1025 _il_wr_prph(il, ALM_SCD_MODE_REG, 0);
1026 _il_wr_prph(il, ALM_SCD_TXFACT_REG, 0);
1029 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
1030 _il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0);
1031 _il_poll_bit(il, FH39_TSSR_TX_STATUS,
1058 il3945_hw_get_temperature(struct il_priv *il)
1060 return _il_rd(il, CSR_UCODE_DRV_GP2);
1068 il3945_hw_reg_txpower_get_temperature(struct il_priv *il)
1070 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1073 temperature = il3945_hw_get_temperature(il);
1085 if (il->last_temperature > 100)
1088 temperature = il->last_temperature;
1106 il3945_is_temp_calib_needed(struct il_priv *il)
1110 il->temperature = il3945_hw_reg_txpower_get_temperature(il);
1111 temp_diff = il->temperature - il->last_temperature;
1132 il->last_temperature = il->temperature;
1325 il3945_hw_reg_set_scan_power(struct il_priv *il, u32 scan_tbl_idx, s32 rate_idx,
1340 power = min(power, il->tx_power_user_lmt);
1382 il3945_send_tx_power(struct il_priv *il)
1387 .channel = il->active.channel,
1392 (test_bit(S_SCAN_HW, &il->status),
1396 chan = le16_to_cpu(il->active.channel);
1398 txpower.band = (il->band == NL80211_BAND_5GHZ) ? 0 : 1;
1399 ch_info = il_get_channel_info(il, il->band, chan);
1402 il->band);
1436 return il_send_cmd_pdu(il, C_TX_PWR_TBL,
1459 il3945_hw_reg_set_new_power(struct il_priv *il, struct il_channel_info *ch_info)
1468 clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers;
1551 il3945_hw_reg_comp_txpower_temp(struct il_priv *il)
1554 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1562 int temperature = il->temperature;
1564 if (il->disable_tx_power_cal || test_bit(S_SCANNING, &il->status)) {
1569 for (i = 0; i < il->channel_count; i++) {
1570 ch_info = &il->channel_info[i];
1599 il->_3945.clip_groups[ch_info->group_idx].clip_powers;
1607 il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
1614 return il->ops->send_tx_power(il);
1618 il3945_hw_reg_set_txpower(struct il_priv *il, s8 power)
1624 if (il->tx_power_user_lmt == power) {
1631 il->tx_power_user_lmt = power;
1635 for (i = 0; i < il->channel_count; i++) {
1636 ch_info = &il->channel_info[i];
1646 il3945_hw_reg_set_new_power(il, ch_info);
1652 il3945_is_temp_calib_needed(il);
1653 il3945_hw_reg_comp_txpower_temp(il);
1659 il3945_send_rxon_assoc(struct il_priv *il)
1670 const struct il_rxon_cmd *rxon1 = &il->staging;
1671 const struct il_rxon_cmd *rxon2 = &il->active;
1681 rxon_assoc.flags = il->staging.flags;
1682 rxon_assoc.filter_flags = il->staging.filter_flags;
1683 rxon_assoc.ofdm_basic_rates = il->staging.ofdm_basic_rates;
1684 rxon_assoc.cck_basic_rates = il->staging.cck_basic_rates;
1687 rc = il_send_cmd_sync(il, &cmd);
1697 il_free_pages(il, cmd.reply_page);
1711 il3945_commit_rxon(struct il_priv *il)
1714 struct il3945_rxon_cmd *active_rxon = (void *)&il->active;
1715 struct il3945_rxon_cmd *staging_rxon = (void *)&il->staging;
1719 if (test_bit(S_EXIT_PENDING, &il->status))
1722 if (!il_is_alive(il))
1730 staging_rxon->flags |= il3945_get_antenna_flags(il);
1732 rc = il_check_rxon_cmd(il);
1741 if (!il_full_rxon_required(il)) {
1742 rc = il_send_rxon_assoc(il);
1754 il_set_tx_power(il, il->tx_power_next, false);
1762 if (il_is_associated(il) && new_assoc) {
1772 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1773 &il->active);
1783 il_clear_ucode_stations(il);
1784 il_restore_stations(il);
1798 il_set_rxon_hwcrypto(il, !il3945_mod_params.sw_crypto);
1801 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1811 il_clear_ucode_stations(il);
1812 il_restore_stations(il);
1817 rc = il_set_tx_power(il, il->tx_power_next, true);
1824 rc = il3945_init_hw_rate_table(il);
1844 il3945_reg_txpower_periodic(struct il_priv *il)
1848 if (!il3945_is_temp_calib_needed(il))
1854 il3945_hw_reg_comp_txpower_temp(il);
1857 queue_delayed_work(il->workqueue, &il->_3945.thermal_periodic,
1864 struct il_priv *il = container_of(work, struct il_priv,
1867 mutex_lock(&il->mutex);
1868 if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL)
1871 il3945_reg_txpower_periodic(il);
1873 mutex_unlock(&il->mutex);
1887 il3945_hw_reg_get_ch_grp_idx(struct il_priv *il,
1890 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1922 il3945_hw_reg_get_matched_power_idx(struct il_priv *il, s8 requested_power,
1926 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1972 il3945_hw_reg_init_channel_groups(struct il_priv *il)
1976 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
2003 clip_pwrs = (s8 *) il->_3945.clip_groups[i].clip_powers;
2041 * Second pass (during init) to set up il->channel_info
2054 il3945_txpower_set_from_eeprom(struct il_priv *il)
2058 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
2071 temperature = il3945_hw_reg_txpower_get_temperature(il);
2072 il->last_temperature = temperature;
2074 il3945_hw_reg_init_channel_groups(il);
2077 for (i = 0, ch_info = il->channel_info; i < il->channel_count;
2084 ch_info->group_idx = il3945_hw_reg_get_ch_grp_idx(il, ch_info);
2088 il->_3945.clip_groups[ch_info->group_idx].clip_powers;
2115 rc = il3945_hw_reg_get_matched_power_idx(il, pwr,
2171 il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
2181 il3945_hw_rxq_stop(struct il_priv *il)
2185 _il_wr(il, FH39_RCSR_CONFIG(0), 0);
2186 ret = _il_poll_bit(il, FH39_RSSR_STATUS,
2197 il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
2201 struct il3945_shared *shared_data = il->_3945.shared_virt;
2205 il_wr(il, FH39_CBCC_CTRL(txq_id), 0);
2206 il_wr(il, FH39_CBCC_BASE(txq_id), 0);
2208 il_wr(il, FH39_TCSR_CONFIG(txq_id),
2216 _il_rd(il, FH39_TSSR_CBB_BASE);
2256 il3945_add_bssid_station(struct il_priv *il, const u8 * addr, u8 * sta_id_r)
2265 ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
2274 spin_lock_irqsave(&il->sta_lock, flags);
2275 il->stations[sta_id].used |= IL_STA_LOCAL;
2276 spin_unlock_irqrestore(&il->sta_lock, flags);
2282 il3945_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
2290 il3945_add_bssid_station(il, vif->bss_conf.bssid,
2295 il3945_sync_sta(il, vif_priv->ibss_bssid_sta_id,
2296 (il->band ==
2299 il3945_rate_scale_init(il->hw, vif_priv->ibss_bssid_sta_id);
2304 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
2312 il3945_init_hw_rate_table(struct il_priv *il)
2324 table[idx].try_cnt = il->retry_rate;
2329 switch (il->band) {
2351 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
2352 il_is_associated(il)) {
2372 rc = il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
2378 return il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
2383 il3945_hw_set_hw_params(struct il_priv *il)
2385 memset((void *)&il->hw_params, 0, sizeof(struct il_hw_params));
2387 il->_3945.shared_virt =
2388 dma_alloc_coherent(&il->pci_dev->dev, sizeof(struct il3945_shared),
2389 &il->_3945.shared_phys, GFP_KERNEL);
2390 if (!il->_3945.shared_virt)
2393 il->hw_params.bcast_id = IL3945_BROADCAST_ID;
2396 il->hw_params.max_txq_num = il->cfg->num_of_queues;
2398 il->hw_params.tfd_size = sizeof(struct il3945_tfd);
2399 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_3K);
2400 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2401 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2402 il->hw_params.max_stations = IL3945_STATION_COUNT;
2404 il->sta_key_max_num = STA_KEY_MAX_NUM;
2406 il->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2407 il->hw_params.max_beacon_itrvl = IL39_MAX_UCODE_BEACON_INTERVAL;
2408 il->hw_params.beacon_time_tsf_bits = IL3945_EXT_BEACON_TIME_POS;
2414 il3945_hw_get_beacon_cmd(struct il_priv *il, struct il3945_frame *frame,
2423 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
2427 il3945_fill_beacon_frame(il, tx_beacon_cmd->frame,
2447 il3945_hw_handler_setup(struct il_priv *il)
2449 il->handlers[C_TX] = il3945_hdl_tx;
2450 il->handlers[N_3945_RX] = il3945_hdl_rx;
2454 il3945_hw_setup_deferred_work(struct il_priv *il)
2456 INIT_DELAYED_WORK(&il->_3945.thermal_periodic,
2461 il3945_hw_cancel_deferred_work(struct il_priv *il)
2463 cancel_delayed_work(&il->_3945.thermal_periodic);
2468 il3945_verify_bsm(struct il_priv *il)
2470 __le32 *image = il->ucode_boot.v_addr;
2471 u32 len = il->ucode_boot.len;
2478 val = il_rd_prph(il, BSM_WR_DWCOUNT_REG);
2481 val = il_rd_prph(il, reg);
2511 il3945_eeprom_acquire_semaphore(struct il_priv *il)
2513 _il_clear_bit(il, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2518 il3945_eeprom_release_semaphore(struct il_priv *il)
2556 il3945_load_bsm(struct il_priv *il)
2558 __le32 *image = il->ucode_boot.v_addr;
2559 u32 len = il->ucode_boot.len;
2580 pinst = il->ucode_init.p_addr;
2581 pdata = il->ucode_init_data.p_addr;
2582 inst_len = il->ucode_init.len;
2583 data_len = il->ucode_init_data.len;
2585 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2586 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2587 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2588 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2594 _il_wr_prph(il, reg_offset, le32_to_cpu(*image));
2596 rc = il3945_verify_bsm(il);
2601 il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
2602 il_wr_prph(il, BSM_WR_MEM_DST_REG, IL39_RTC_INST_LOWER_BOUND);
2603 il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2607 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
2611 done = il_rd_prph(il, BSM_WR_CTRL_REG);
2625 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);