Lines Matching defs:il
80 * @il: eeprom and antenna fields are used to determine antenna flags
82 * il->eeprom39 is used to determine if antenna AUX/MAIN are reversed
90 il3945_get_antenna_flags(const struct il_priv *il)
92 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
117 il3945_set_ccmp_dynamic_key_info(struct il_priv *il,
127 if (sta_id == il->hw_params.bcast_id)
134 spin_lock_irqsave(&il->sta_lock, flags);
135 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
136 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
137 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
139 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
141 if ((il->stations[sta_id].sta.key.
143 il->stations[sta_id].sta.key.key_offset =
144 il_get_free_ucode_key_idx(il);
148 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
151 il->stations[sta_id].sta.key.key_flags = key_flags;
152 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
153 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
157 ret = il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
159 spin_unlock_irqrestore(&il->sta_lock, flags);
165 il3945_set_tkip_dynamic_key_info(struct il_priv *il,
172 il3945_set_wep_dynamic_key_info(struct il_priv *il,
179 il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id)
184 spin_lock_irqsave(&il->sta_lock, flags);
185 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
186 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
187 il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
188 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
189 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
190 memcpy(&sta_cmd, &il->stations[sta_id].sta,
192 spin_unlock_irqrestore(&il->sta_lock, flags);
195 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
199 il3945_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
208 ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
211 ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id);
215 ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id);
229 il3945_remove_static_key(struct il_priv *il)
235 il3945_set_static_key(struct il_priv *il, struct ieee80211_key_conf *key)
246 il3945_clear_free_frames(struct il_priv *il)
250 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
252 while (!list_empty(&il->free_frames)) {
253 element = il->free_frames.next;
256 il->frames_count--;
259 if (il->frames_count) {
261 il->frames_count);
262 il->frames_count = 0;
267 il3945_get_free_frame(struct il_priv *il)
271 if (list_empty(&il->free_frames)) {
278 il->frames_count++;
282 element = il->free_frames.next;
288 il3945_free_frame(struct il_priv *il, struct il3945_frame *frame)
291 list_add(&frame->list, &il->free_frames);
295 il3945_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
299 if (!il_is_associated(il) || !il->beacon_skb)
302 if (il->beacon_skb->len > left)
305 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
307 return il->beacon_skb->len;
311 il3945_send_beacon_cmd(struct il_priv *il)
318 frame = il3945_get_free_frame(il);
326 rate = il_get_lowest_plcp(il);
328 frame_size = il3945_hw_get_beacon_cmd(il, frame, rate);
330 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
332 il3945_free_frame(il, frame);
338 il3945_unset_hw_params(struct il_priv *il)
340 if (il->_3945.shared_virt)
341 dma_free_coherent(&il->pci_dev->dev,
343 il->_3945.shared_virt, il->_3945.shared_phys);
347 il3945_build_tx_cmd_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
352 struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo;
391 il3945_build_tx_cmd_basic(struct il_priv *il, struct il_device_cmd *cmd,
424 il_tx_cmd_protection(il, info, fc, &tx_flags);
445 il3945_tx_skb(struct il_priv *il,
467 spin_lock_irqsave(&il->lock, flags);
468 if (il_is_rfkill(il)) {
473 if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) ==
490 spin_unlock_irqrestore(&il->lock, flags);
495 sta_id = il_sta_id_or_broadcast(il, sta);
511 txq = &il->txq[txq_id];
517 spin_lock_irqsave(&il->lock, flags);
545 il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id);
548 il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id);
550 il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id);
575 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
577 if (unlikely(pci_dma_mapping_error(il->pci_dev, txcmd_phys)))
585 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
587 if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr)))
593 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
597 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen, 0,
607 il_update_stats(il, true, fc, skb->len);
611 il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd));
612 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr,
617 il_txq_update_write_ptr(il, txq);
618 spin_unlock_irqrestore(&il->lock, flags);
620 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
622 spin_lock_irqsave(&il->lock, flags);
624 il_txq_update_write_ptr(il, txq);
625 spin_unlock_irqrestore(&il->lock, flags);
628 il_stop_queue(il, txq);
634 spin_unlock_irqrestore(&il->lock, flags);
640 il3945_get_measurement(struct il_priv *il,
655 if (il_is_associated(il))
657 il_usecs_to_beacons(il,
659 il->_3945.last_tsf,
660 le16_to_cpu(il->timing.beacon_interval));
671 if (il_is_associated(il))
673 il_add_beacon_time(il, il->_3945.last_beacon_time, add_time,
674 le16_to_cpu(il->timing.beacon_interval));
681 if (il->active.flags & RXON_FLG_BAND_24G_MSK)
686 rc = il_send_cmd_sync(il, &cmd);
702 il->measurement_status &= ~MEASUREMENT_READY;
704 il->measurement_status |= MEASUREMENT_ACTIVE;
713 il_free_pages(il, cmd.reply_page);
719 il3945_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
732 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
734 pwork = &il->init_alive_start;
737 memcpy(&il->card_alive, &pkt->u.alive_frame,
739 pwork = &il->alive_start;
740 il3945_disable_events(il);
746 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
752 il3945_hdl_add_sta(struct il_priv *il, struct il_rx_buf *rxb)
762 il3945_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
776 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
783 il3945_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
787 unsigned long status = il->status;
793 _il_wr(il, CSR_UCODE_DRV_GP1_SET, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
796 set_bit(S_RFKILL, &il->status);
798 clear_bit(S_RFKILL, &il->status);
800 il_scan_cancel(il);
803 test_bit(S_RFKILL, &il->status)))
804 wiphy_rfkill_set_hw_state(il->hw->wiphy,
805 test_bit(S_RFKILL, &il->status));
807 wake_up(&il->wait_command_queue);
820 il3945_setup_handlers(struct il_priv *il)
822 il->handlers[N_ALIVE] = il3945_hdl_alive;
823 il->handlers[C_ADD_STA] = il3945_hdl_add_sta;
824 il->handlers[N_ERROR] = il_hdl_error;
825 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
826 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
827 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
828 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
829 il->handlers[N_BEACON] = il3945_hdl_beacon;
836 il->handlers[C_STATS] = il3945_hdl_c_stats;
837 il->handlers[N_STATS] = il3945_hdl_stats;
839 il_setup_rx_scan_handlers(il);
840 il->handlers[N_CARD_STATE] = il3945_hdl_card_state;
843 il3945_hw_handler_setup(il);
914 il3945_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
931 il3945_rx_queue_restock(struct il_priv *il)
933 struct il_rx_queue *rxq = &il->rxq;
947 il3945_dma_addr2rbd_ptr(il, rxb->page_dma);
956 queue_work(il->workqueue, &il->rx_replenish);
965 il_rx_queue_update_write_ptr(il, rxq);
978 il3945_rx_allocate(struct il_priv *il, gfp_t priority)
980 struct il_rx_queue *rxq = &il->rxq;
999 if (il->hw_params.rx_page_order > 0)
1003 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
1020 pci_map_page(il->pci_dev, page, 0,
1021 PAGE_SIZE << il->hw_params.rx_page_order,
1024 if (unlikely(pci_dma_mapping_error(il->pci_dev, page_dma))) {
1025 __free_pages(page, il->hw_params.rx_page_order);
1033 pci_unmap_page(il->pci_dev, page_dma,
1034 PAGE_SIZE << il->hw_params.rx_page_order,
1036 __free_pages(page, il->hw_params.rx_page_order);
1048 il->alloc_rxb_page++;
1055 il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
1067 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
1068 PAGE_SIZE << il->hw_params.rx_page_order,
1070 __il_free_pages(il, rxq->pool[i].page);
1087 struct il_priv *il = data;
1090 il3945_rx_allocate(il, GFP_KERNEL);
1092 spin_lock_irqsave(&il->lock, flags);
1093 il3945_rx_queue_restock(il);
1094 spin_unlock_irqrestore(&il->lock, flags);
1098 il3945_rx_replenish_now(struct il_priv *il)
1100 il3945_rx_allocate(il, GFP_ATOMIC);
1102 il3945_rx_queue_restock(il);
1111 il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
1116 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
1117 PAGE_SIZE << il->hw_params.rx_page_order,
1119 __il_free_pages(il, rxq->pool[i].page);
1124 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1126 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
1173 * Uses the il->handlers callback function array to invoke
1178 il3945_rx_handle(struct il_priv *il)
1182 struct il_rx_queue *rxq = &il->rxq;
1218 pci_unmap_page(il->pci_dev, rxb->page_dma,
1219 PAGE_SIZE << il->hw_params.rx_page_order,
1226 reclaim = il_need_reclaim(il, pkt);
1231 if (il->handlers[pkt->hdr.cmd]) {
1234 il->isr_stats.handlers[pkt->hdr.cmd]++;
1235 il->handlers[pkt->hdr.cmd] (il, rxb);
1254 il_tx_cmd_complete(il, rxb);
1265 pci_map_page(il->pci_dev, rxb->page, 0,
1266 PAGE_SIZE << il->hw_params.
1268 if (unlikely(pci_dma_mapping_error(il->pci_dev,
1270 __il_free_pages(il, rxb->page);
1289 il3945_rx_replenish_now(il);
1298 il3945_rx_replenish_now(il);
1300 il3945_rx_queue_restock(il);
1305 il3945_synchronize_irq(struct il_priv *il)
1308 synchronize_irq(il->pci_dev->irq);
1309 tasklet_kill(&il->irq_tasklet);
1337 il3945_dump_nic_error_log(struct il_priv *il)
1343 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
1350 count = il_read_targ_mem(il, base);
1354 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
1362 desc = il_read_targ_mem(il, base + i);
1363 time = il_read_targ_mem(il, base + i + 1 * sizeof(u32));
1364 blink1 = il_read_targ_mem(il, base + i + 2 * sizeof(u32));
1365 blink2 = il_read_targ_mem(il, base + i + 3 * sizeof(u32));
1366 ilink1 = il_read_targ_mem(il, base + i + 4 * sizeof(u32));
1367 ilink2 = il_read_targ_mem(il, base + i + 5 * sizeof(u32));
1368 data1 = il_read_targ_mem(il, base + i + 6 * sizeof(u32));
1379 struct il_priv *il = from_tasklet(il, t, irq_tasklet);
1387 spin_lock_irqsave(&il->lock, flags);
1392 inta = _il_rd(il, CSR_INT);
1393 _il_wr(il, CSR_INT, inta);
1398 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1399 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
1402 if (il_get_debug_level(il) & IL_DL_ISR) {
1404 inta_mask = _il_rd(il, CSR_INT_MASK);
1410 spin_unlock_irqrestore(&il->lock, flags);
1426 il_disable_interrupts(il);
1428 il->isr_stats.hw++;
1429 il_irq_handle_error(il);
1436 if (il_get_debug_level(il) & (IL_DL_ISR)) {
1441 il->isr_stats.sch++;
1447 il->isr_stats.alive++;
1458 il->isr_stats.sw++;
1459 il_irq_handle_error(il);
1466 il_rx_queue_update_write_ptr(il, &il->rxq);
1468 spin_lock_irqsave(&il->lock, flags);
1469 il_txq_update_write_ptr(il, &il->txq[0]);
1470 il_txq_update_write_ptr(il, &il->txq[1]);
1471 il_txq_update_write_ptr(il, &il->txq[2]);
1472 il_txq_update_write_ptr(il, &il->txq[3]);
1473 il_txq_update_write_ptr(il, &il->txq[4]);
1474 spin_unlock_irqrestore(&il->lock, flags);
1476 il->isr_stats.wakeup++;
1484 il3945_rx_handle(il);
1485 il->isr_stats.rx++;
1491 il->isr_stats.tx++;
1493 _il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
1494 il_wr(il, FH39_TCSR_CREDIT(FH39_SRVC_CHNL), 0x0);
1500 il->isr_stats.unhandled++;
1503 if (inta & ~il->inta_mask) {
1505 inta & ~il->inta_mask);
1511 if (test_bit(S_INT_ENABLED, &il->status))
1512 il_enable_interrupts(il);
1515 if (il_get_debug_level(il) & (IL_DL_ISR)) {
1516 inta = _il_rd(il, CSR_INT);
1517 inta_mask = _il_rd(il, CSR_INT_MASK);
1518 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1526 il3945_get_channels_for_scan(struct il_priv *il, enum nl80211_band band,
1538 sband = il_get_hw_mode(il, band);
1542 active_dwell = il_get_active_dwell_time(il, band, n_probes);
1543 passive_dwell = il_get_passive_dwell_time(il, band, vif);
1548 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
1549 chan = il->scan_request->channels[i];
1556 ch_info = il_get_channel_info(il, band, scan_ch->channel);
1571 if (IL_UCODE_API(il->ucode_ver) == 1)
1582 if (IL_UCODE_API(il->ucode_ver) >= 2) {
1620 il3945_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
1647 il3945_dealloc_ucode_pci(struct il_priv *il)
1649 il_free_fw_desc(il->pci_dev, &il->ucode_code);
1650 il_free_fw_desc(il->pci_dev, &il->ucode_data);
1651 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
1652 il_free_fw_desc(il->pci_dev, &il->ucode_init);
1653 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
1654 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
1662 il3945_verify_inst_full(struct il_priv *il, __le32 * image, u32 len)
1671 il_wr(il, HBUS_TARG_MEM_RADDR, IL39_RTC_INST_LOWER_BOUND);
1678 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1702 il3945_verify_inst_sparse(struct il_priv *il, __le32 * image, u32 len)
1715 il_wr(il, HBUS_TARG_MEM_RADDR, i + IL39_RTC_INST_LOWER_BOUND);
1716 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1738 il3945_verify_ucode(struct il_priv *il)
1745 image = (__le32 *) il->ucode_boot.v_addr;
1746 len = il->ucode_boot.len;
1747 rc = il3945_verify_inst_sparse(il, image, len);
1754 image = (__le32 *) il->ucode_init.v_addr;
1755 len = il->ucode_init.len;
1756 rc = il3945_verify_inst_sparse(il, image, len);
1763 image = (__le32 *) il->ucode_code.v_addr;
1764 len = il->ucode_code.len;
1765 rc = il3945_verify_inst_sparse(il, image, len);
1776 image = (__le32 *) il->ucode_boot.v_addr;
1777 len = il->ucode_boot.len;
1778 rc = il3945_verify_inst_full(il, image, len);
1784 il3945_nic_start(struct il_priv *il)
1787 _il_wr(il, CSR_RESET, 0);
1820 il3945_read_ucode(struct il_priv *il)
1826 const char *name_pre = il->cfg->fw_name_pre;
1827 const unsigned int api_max = il->cfg->ucode_api_max;
1828 const unsigned int api_min = il->cfg->ucode_api_min;
1838 ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev);
1870 il->ucode_ver = le32_to_cpu(ucode->ver);
1871 api_ver = IL_UCODE_API(il->ucode_ver);
1887 il->ucode_ver = 0;
1898 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
1899 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
1901 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
1902 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
1903 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
1904 IL_UCODE_SERIAL(il->ucode_ver));
1906 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
1960 il->ucode_code.len = inst_size;
1961 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
1963 il->ucode_data.len = data_size;
1964 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
1966 il->ucode_data_backup.len = data_size;
1967 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
1969 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
1970 !il->ucode_data_backup.v_addr)
1975 il->ucode_init.len = init_size;
1976 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
1978 il->ucode_init_data.len = init_data_size;
1979 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
1981 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
1987 il->ucode_boot.len = boot_size;
1988 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
1990 if (!il->ucode_boot.v_addr)
1999 memcpy(il->ucode_code.v_addr, src, len);
2003 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
2009 memcpy(il->ucode_data.v_addr, src, len);
2010 memcpy(il->ucode_data_backup.v_addr, src, len);
2017 memcpy(il->ucode_init.v_addr, src, len);
2025 memcpy(il->ucode_init_data.v_addr, src, len);
2032 memcpy(il->ucode_boot.v_addr, src, len);
2041 il3945_dealloc_ucode_pci(il);
2060 il3945_set_ucode_ptrs(struct il_priv *il)
2066 pinst = il->ucode_code.p_addr;
2067 pdata = il->ucode_data_backup.p_addr;
2070 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2071 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2072 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, il->ucode_data.len);
2076 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
2077 il->ucode_code.len | BSM_DRAM_INST_LOAD);
2092 il3945_init_alive_start(struct il_priv *il)
2095 if (il->card_alive_init.is_valid != UCODE_VALID_OK) {
2105 if (il3945_verify_ucode(il)) {
2116 if (il3945_set_ucode_ptrs(il)) {
2125 queue_work(il->workqueue, &il->restart);
2134 il3945_alive_start(struct il_priv *il)
2141 if (il->card_alive.is_valid != UCODE_VALID_OK) {
2151 if (il3945_verify_ucode(il)) {
2158 rfkill = il_rd_prph(il, APMG_RFKILL_REG);
2162 clear_bit(S_RFKILL, &il->status);
2165 while (il3945_hw_get_temperature(il) == 0) {
2174 set_bit(S_RFKILL, &il->status);
2177 set_bit(S_ALIVE, &il->status);
2180 il_setup_watchdog(il);
2182 if (il_is_rfkill(il))
2185 ieee80211_wake_queues(il->hw);
2187 il->active_rate = RATES_MASK_3945;
2189 il_power_update_mode(il, true);
2191 if (il_is_associated(il)) {
2193 (struct il3945_rxon_cmd *)(&il->active);
2195 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2199 il_connection_init_rx_config(il);
2203 il_send_bt_config(il);
2205 set_bit(S_READY, &il->status);
2208 il3945_commit_rxon(il);
2210 il3945_reg_txpower_periodic(il);
2213 wake_up(&il->wait_command_queue);
2218 queue_work(il->workqueue, &il->restart);
2221 static void il3945_cancel_deferred_work(struct il_priv *il);
2224 __il3945_down(struct il_priv *il)
2231 il_scan_cancel_timeout(il, 200);
2233 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
2237 del_timer_sync(&il->watchdog);
2240 il_clear_ucode_stations(il);
2241 il_dealloc_bcast_stations(il);
2242 il_clear_driver_stations(il);
2245 wake_up_all(&il->wait_command_queue);
2250 clear_bit(S_EXIT_PENDING, &il->status);
2253 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2256 spin_lock_irqsave(&il->lock, flags);
2257 il_disable_interrupts(il);
2258 spin_unlock_irqrestore(&il->lock, flags);
2259 il3945_synchronize_irq(il);
2261 if (il->mac80211_registered)
2262 ieee80211_stop_queues(il->hw);
2266 if (!il_is_init(il)) {
2267 il->status =
2268 test_bit(S_RFKILL, &il->status) << S_RFKILL |
2269 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2270 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2276 il->status &=
2277 test_bit(S_RFKILL, &il->status) << S_RFKILL |
2278 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2279 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
2280 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2287 spin_lock_irq(&il->reg_lock);
2290 il3945_hw_txq_ctx_stop(il);
2291 il3945_hw_rxq_stop(il);
2293 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2296 _il_apm_stop(il);
2298 spin_unlock_irq(&il->reg_lock);
2300 il3945_hw_txq_ctx_free(il);
2302 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
2303 dev_kfree_skb(il->beacon_skb);
2304 il->beacon_skb = NULL;
2307 il3945_clear_free_frames(il);
2311 il3945_down(struct il_priv *il)
2313 mutex_lock(&il->mutex);
2314 __il3945_down(il);
2315 mutex_unlock(&il->mutex);
2317 il3945_cancel_deferred_work(il);
2323 il3945_alloc_bcast_station(struct il_priv *il)
2328 spin_lock_irqsave(&il->sta_lock, flags);
2329 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
2332 spin_unlock_irqrestore(&il->sta_lock, flags);
2337 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
2338 il->stations[sta_id].used |= IL_STA_BCAST;
2339 spin_unlock_irqrestore(&il->sta_lock, flags);
2345 __il3945_up(struct il_priv *il)
2349 rc = il3945_alloc_bcast_station(il);
2353 if (test_bit(S_EXIT_PENDING, &il->status)) {
2358 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
2364 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2365 clear_bit(S_RFKILL, &il->status);
2367 set_bit(S_RFKILL, &il->status);
2371 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2373 rc = il3945_hw_nic_init(il);
2380 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2381 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2384 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2385 il_enable_interrupts(il);
2388 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2389 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2394 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
2395 il->ucode_data.len);
2398 if (test_bit(S_RFKILL, &il->status))
2406 rc = il->ops->load_ucode(il);
2414 il3945_nic_start(il);
2421 set_bit(S_EXIT_PENDING, &il->status);
2422 __il3945_down(il);
2423 clear_bit(S_EXIT_PENDING, &il->status);
2440 struct il_priv *il =
2443 mutex_lock(&il->mutex);
2444 if (test_bit(S_EXIT_PENDING, &il->status))
2447 il3945_init_alive_start(il);
2449 mutex_unlock(&il->mutex);
2455 struct il_priv *il =
2458 mutex_lock(&il->mutex);
2459 if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL)
2462 il3945_alive_start(il);
2464 mutex_unlock(&il->mutex);
2476 struct il_priv *il =
2478 bool old_rfkill = test_bit(S_RFKILL, &il->status);
2480 !(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2484 set_bit(S_RFKILL, &il->status);
2486 clear_bit(S_RFKILL, &il->status);
2488 wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill);
2496 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2502 il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
2516 lockdep_assert_held(&il->mutex);
2518 if (!il->scan_cmd) {
2519 il->scan_cmd =
2522 if (!il->scan_cmd) {
2527 scan = il->scan_cmd;
2533 if (il_is_associated(il)) {
2563 if (il->scan_request->n_ssids) {
2566 for (i = 0; i < il->scan_request->n_ssids; i++) {
2568 if (!il->scan_request->ssids[i].ssid_len)
2572 il->scan_request->ssids[i].ssid_len;
2574 il->scan_request->ssids[i].ssid,
2575 il->scan_request->ssids[i].ssid_len);
2586 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
2591 switch (il->scan_band) {
2615 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
2616 vif->addr, il->scan_request->ie,
2617 il->scan_request->ie_len,
2622 scan->flags |= il3945_get_antenna_flags(il);
2625 il3945_get_channels_for_scan(il, band, is_active, n_probes,
2638 set_bit(S_SCAN_HW, &il->status);
2639 ret = il_send_cmd_sync(il, &cmd);
2641 clear_bit(S_SCAN_HW, &il->status);
2646 il3945_post_scan(struct il_priv *il)
2652 if (memcmp(&il->staging, &il->active, sizeof(il->staging)))
2653 il3945_commit_rxon(il);
2659 struct il_priv *il = container_of(data, struct il_priv, restart);
2661 if (test_bit(S_EXIT_PENDING, &il->status))
2664 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
2665 mutex_lock(&il->mutex);
2666 il->is_open = 0;
2667 mutex_unlock(&il->mutex);
2668 il3945_down(il);
2669 ieee80211_restart_hw(il->hw);
2671 il3945_down(il);
2673 mutex_lock(&il->mutex);
2674 if (test_bit(S_EXIT_PENDING, &il->status)) {
2675 mutex_unlock(&il->mutex);
2679 __il3945_up(il);
2680 mutex_unlock(&il->mutex);
2687 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
2689 mutex_lock(&il->mutex);
2690 if (test_bit(S_EXIT_PENDING, &il->status))
2693 il3945_rx_replenish(il);
2695 mutex_unlock(&il->mutex);
2699 il3945_post_associate(struct il_priv *il)
2703 if (!il->vif || !il->is_open)
2706 D_ASSOC("Associated as %d to: %pM\n", il->vif->bss_conf.aid,
2707 il->active.bssid_addr);
2709 if (test_bit(S_EXIT_PENDING, &il->status))
2712 il_scan_cancel_timeout(il, 200);
2714 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2715 il3945_commit_rxon(il);
2717 rc = il_send_rxon_timing(il);
2721 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2723 il->staging.assoc_id = cpu_to_le16(il->vif->bss_conf.aid);
2725 D_ASSOC("assoc id %d beacon interval %d\n", il->vif->bss_conf.aid,
2726 il->vif->bss_conf.beacon_int);
2728 if (il->vif->bss_conf.use_short_preamble)
2729 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2731 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2733 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2734 if (il->vif->bss_conf.use_short_slot)
2735 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2737 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2740 il3945_commit_rxon(il);
2742 switch (il->vif->type) {
2744 il3945_rate_scale_init(il->hw, IL_AP_ID);
2747 il3945_send_beacon_cmd(il);
2751 il->vif->type);
2767 struct il_priv *il = hw->priv;
2771 mutex_lock(&il->mutex);
2777 if (!il->ucode_code.len) {
2778 ret = il3945_read_ucode(il);
2781 mutex_unlock(&il->mutex);
2786 ret = __il3945_up(il);
2788 mutex_unlock(&il->mutex);
2797 ret = wait_event_timeout(il->wait_command_queue,
2798 test_bit(S_READY, &il->status),
2801 if (!test_bit(S_READY, &il->status)) {
2811 cancel_delayed_work(&il->_3945.rfkill_poll);
2813 il->is_open = 1;
2818 il->is_open = 0;
2826 struct il_priv *il = hw->priv;
2830 if (!il->is_open) {
2835 il->is_open = 0;
2837 il3945_down(il);
2839 flush_workqueue(il->workqueue);
2842 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2853 struct il_priv *il = hw->priv;
2860 if (il3945_tx_skb(il, control->sta, skb))
2867 il3945_config_ap(struct il_priv *il)
2869 struct ieee80211_vif *vif = il->vif;
2872 if (test_bit(S_EXIT_PENDING, &il->status))
2876 if (!(il_is_associated(il))) {
2879 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2880 il3945_commit_rxon(il);
2883 rc = il_send_rxon_timing(il);
2888 il->staging.assoc_id = 0;
2891 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2893 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2895 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2897 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2899 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2902 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2903 il3945_commit_rxon(il);
2905 il3945_send_beacon_cmd(il);
2913 struct il_priv *il = hw->priv;
2935 static_key = !il_is_associated(il);
2938 sta_id = il_sta_id_or_broadcast(il, sta);
2945 mutex_lock(&il->mutex);
2946 il_scan_cancel_timeout(il, 100);
2951 ret = il3945_set_static_key(il, key);
2953 ret = il3945_set_dynamic_key(il, key, sta_id);
2958 ret = il3945_remove_static_key(il);
2960 ret = il3945_clear_sta_key_info(il, sta_id);
2968 mutex_unlock(&il->mutex);
2977 struct il_priv *il = hw->priv;
2983 mutex_lock(&il->mutex);
2987 ret = il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
2991 mutex_unlock(&il->mutex);
2999 il3945_rs_rate_init(il, sta, sta_id);
3000 mutex_unlock(&il->mutex);
3009 struct il_priv *il = hw->priv;
3028 mutex_lock(&il->mutex);
3030 il->staging.filter_flags &= ~filter_nand;
3031 il->staging.filter_flags |= filter_or;
3039 mutex_unlock(&il->mutex);
3075 struct il_priv *il = dev_get_drvdata(d);
3076 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
3083 struct il_priv *il = dev_get_drvdata(d);
3091 il->debug_level = val;
3105 struct il_priv *il = dev_get_drvdata(d);
3107 if (!il_is_alive(il))
3110 return sprintf(buf, "%d\n", il3945_hw_get_temperature(il));
3118 struct il_priv *il = dev_get_drvdata(d);
3119 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
3126 struct il_priv *il = dev_get_drvdata(d);
3134 il3945_hw_reg_set_txpower(il, val);
3144 struct il_priv *il = dev_get_drvdata(d);
3146 return sprintf(buf, "0x%04X\n", il->active.flags);
3153 struct il_priv *il = dev_get_drvdata(d);
3156 mutex_lock(&il->mutex);
3157 if (le32_to_cpu(il->staging.flags) != flags) {
3159 if (il_scan_cancel_timeout(il, 100))
3163 il->staging.flags = cpu_to_le32(flags);
3164 il3945_commit_rxon(il);
3167 mutex_unlock(&il->mutex);
3178 struct il_priv *il = dev_get_drvdata(d);
3180 return sprintf(buf, "0x%04X\n", le32_to_cpu(il->active.filter_flags));
3187 struct il_priv *il = dev_get_drvdata(d);
3190 mutex_lock(&il->mutex);
3191 if (le32_to_cpu(il->staging.filter_flags) != filter_flags) {
3193 if (il_scan_cancel_timeout(il, 100))
3198 il->staging.filter_flags = cpu_to_le32(filter_flags);
3199 il3945_commit_rxon(il);
3202 mutex_unlock(&il->mutex);
3214 struct il_priv *il = dev_get_drvdata(d);
3220 spin_lock_irqsave(&il->lock, flags);
3221 if (!(il->measurement_status & MEASUREMENT_READY)) {
3222 spin_unlock_irqrestore(&il->lock, flags);
3225 memcpy(&measure_report, &il->measure_report, size);
3226 il->measurement_status = 0;
3227 spin_unlock_irqrestore(&il->lock, flags);
3247 struct il_priv *il = dev_get_drvdata(d);
3249 .channel = le16_to_cpu(il->active.channel),
3250 .start_time = cpu_to_le64(il->_3945.last_tsf),
3273 il3945_get_measurement(il, ¶ms, type);
3285 struct il_priv *il = dev_get_drvdata(d);
3287 il->retry_rate = simple_strtoul(buf, NULL, 0);
3288 if (il->retry_rate <= 0)
3289 il->retry_rate = 1;
3298 struct il_priv *il = dev_get_drvdata(d);
3299 return sprintf(buf, "%d", il->retry_rate);
3317 struct il_priv *il = dev_get_drvdata(d);
3319 if (!il_is_alive(il))
3329 struct il_priv *il __maybe_unused = dev_get_drvdata(d);
3354 struct il_priv *il = dev_get_drvdata(d);
3355 if (!il_is_alive(il))
3357 return sprintf(buf, "0x%08x\n", (int)il->status);
3366 struct il_priv *il = dev_get_drvdata(d);
3370 il3945_dump_nic_error_log(il);
3384 il3945_setup_deferred_work(struct il_priv *il)
3386 il->workqueue = create_singlethread_workqueue(DRV_NAME);
3387 if (!il->workqueue)
3390 init_waitqueue_head(&il->wait_command_queue);
3392 INIT_WORK(&il->restart, il3945_bg_restart);
3393 INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish);
3394 INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start);
3395 INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start);
3396 INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll);
3398 il_setup_scan_deferred_work(il);
3400 il3945_hw_setup_deferred_work(il);
3402 timer_setup(&il->watchdog, il_bg_watchdog, 0);
3404 tasklet_setup(&il->irq_tasklet, il3945_irq_tasklet);
3410 il3945_cancel_deferred_work(struct il_priv *il)
3412 il3945_hw_cancel_deferred_work(il);
3414 cancel_delayed_work_sync(&il->init_alive_start);
3415 cancel_delayed_work(&il->alive_start);
3417 il_cancel_scan_deferred_work(il);
3463 il3945_init_drv(struct il_priv *il)
3466 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
3468 il->retry_rate = 1;
3469 il->beacon_skb = NULL;
3471 spin_lock_init(&il->sta_lock);
3472 spin_lock_init(&il->hcmd_lock);
3474 INIT_LIST_HEAD(&il->free_frames);
3476 mutex_init(&il->mutex);
3478 il->ieee_channels = NULL;
3479 il->ieee_rates = NULL;
3480 il->band = NL80211_BAND_2GHZ;
3482 il->iw_mode = NL80211_IFTYPE_STATION;
3483 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
3486 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
3494 ret = il_init_channel_map(il);
3501 if (il3945_txpower_set_from_eeprom(il)) {
3506 ret = il_init_geos(il);
3511 il3945_init_hw_rates(il, il->ieee_rates);
3516 il_free_channel_map(il);
3524 il3945_setup_mac(struct il_priv *il)
3527 struct ieee80211_hw *hw = il->hw;
3555 if (il->bands[NL80211_BAND_2GHZ].n_channels)
3556 il->hw->wiphy->bands[NL80211_BAND_2GHZ] =
3557 &il->bands[NL80211_BAND_2GHZ];
3559 if (il->bands[NL80211_BAND_5GHZ].n_channels)
3560 il->hw->wiphy->bands[NL80211_BAND_5GHZ] =
3561 &il->bands[NL80211_BAND_5GHZ];
3563 il_leds_init(il);
3565 wiphy_ext_feature_set(il->hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
3567 ret = ieee80211_register_hw(il->hw);
3572 il->mac80211_registered = 1;
3581 struct il_priv *il;
3596 il = hw->priv;
3597 il->hw = hw;
3600 il->cmd_queue = IL39_CMD_QUEUE_NUM;
3603 il->cfg = cfg;
3604 il->ops = &il3945_ops;
3606 il->debugfs_ops = &il3945_debugfs_ops;
3608 il->pci_dev = pdev;
3609 il->inta_mask = CSR_INI_SET_MASK;
3633 pci_set_drvdata(pdev, il);
3641 il->hw_base = pci_ioremap_bar(pdev, 0);
3642 if (!il->hw_base) {
3649 D_INFO("pci_resource_base = %p\n", il->hw_base);
3658 spin_lock_init(&il->reg_lock);
3659 spin_lock_init(&il->lock);
3666 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3673 err = il_eeprom_init(il);
3679 eeprom = (struct il3945_eeprom *)il->eeprom;
3681 SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address);
3687 err = il3945_hw_set_hw_params(il);
3694 * 6. Setup il
3697 err = il3945_init_drv(il);
3703 IL_INFO("Detected Intel Wireless WiFi Link %s\n", il->cfg->name);
3709 spin_lock_irqsave(&il->lock, flags);
3710 il_disable_interrupts(il);
3711 spin_unlock_irqrestore(&il->lock, flags);
3713 pci_enable_msi(il->pci_dev);
3715 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
3717 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
3727 il_set_rxon_channel(il, &il->bands[NL80211_BAND_2GHZ].channels[5]);
3728 err = il3945_setup_deferred_work(il);
3732 il3945_setup_handlers(il);
3733 il_power_initialize(il);
3739 il_enable_interrupts(il);
3741 err = il3945_setup_mac(il);
3745 il_dbgfs_register(il, DRV_NAME);
3748 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, 2 * HZ);
3753 destroy_workqueue(il->workqueue);
3754 il->workqueue = NULL;
3758 free_irq(il->pci_dev->irq, il);
3760 pci_disable_msi(il->pci_dev);
3761 il_free_geos(il);
3762 il_free_channel_map(il);
3764 il3945_unset_hw_params(il);
3766 il_eeprom_free(il);
3768 iounmap(il->hw_base);
3774 ieee80211_free_hw(il->hw);
3782 struct il_priv *il = pci_get_drvdata(pdev);
3785 if (!il)
3790 il_dbgfs_unregister(il);
3792 set_bit(S_EXIT_PENDING, &il->status);
3794 il_leds_exit(il);
3796 if (il->mac80211_registered) {
3797 ieee80211_unregister_hw(il->hw);
3798 il->mac80211_registered = 0;
3800 il3945_down(il);
3810 il_apm_stop(il);
3815 spin_lock_irqsave(&il->lock, flags);
3816 il_disable_interrupts(il);
3817 spin_unlock_irqrestore(&il->lock, flags);
3819 il3945_synchronize_irq(il);
3823 cancel_delayed_work_sync(&il->_3945.rfkill_poll);
3825 il3945_dealloc_ucode_pci(il);
3827 if (il->rxq.bd)
3828 il3945_rx_queue_free(il, &il->rxq);
3829 il3945_hw_txq_ctx_free(il);
3831 il3945_unset_hw_params(il);
3834 flush_workqueue(il->workqueue);
3837 * il->workqueue... so we can't take down the workqueue
3839 destroy_workqueue(il->workqueue);
3840 il->workqueue = NULL;
3842 free_irq(pdev->irq, il);
3845 iounmap(il->hw_base);
3849 il_free_channel_map(il);
3850 il_free_geos(il);
3851 kfree(il->scan_cmd);
3852 dev_kfree_skb(il->beacon_skb);
3853 ieee80211_free_hw(il->hw);