Lines Matching refs:dev
362 static void b43_wireless_core_exit(struct b43_wldev *dev);
363 static int b43_wireless_core_init(struct b43_wldev *dev);
364 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
365 static int b43_wireless_core_start(struct b43_wldev *dev);
464 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
470 macctl = b43_read32(dev, B43_MMIO_MACCTL);
474 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
475 b43_write32(dev, B43_MMIO_RAM_DATA, val);
478 static inline void b43_shm_control_word(struct b43_wldev *dev,
487 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
490 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
498 b43_shm_control_word(dev, routing, offset >> 2);
499 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
500 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
501 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
507 b43_shm_control_word(dev, routing, offset);
508 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
513 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
521 b43_shm_control_word(dev, routing, offset >> 2);
522 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
528 b43_shm_control_word(dev, routing, offset);
529 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
534 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
540 b43_shm_control_word(dev, routing, offset >> 2);
541 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
543 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
544 b43_write16(dev, B43_MMIO_SHM_DATA,
550 b43_shm_control_word(dev, routing, offset);
551 b43_write32(dev, B43_MMIO_SHM_DATA, value);
554 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
560 b43_shm_control_word(dev, routing, offset >> 2);
561 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
566 b43_shm_control_word(dev, routing, offset);
567 b43_write16(dev, B43_MMIO_SHM_DATA, value);
571 u64 b43_hf_read(struct b43_wldev *dev)
575 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
577 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
579 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
585 void b43_hf_write(struct b43_wldev *dev, u64 value)
592 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
593 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
594 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
598 static u16 b43_fwcapa_read(struct b43_wldev *dev)
600 B43_WARN_ON(!dev->fw.opensource);
601 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
604 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
608 B43_WARN_ON(dev->dev->core_rev < 3);
612 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
613 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
620 static void b43_time_lock(struct b43_wldev *dev)
622 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
624 b43_read32(dev, B43_MMIO_MACCTL);
627 static void b43_time_unlock(struct b43_wldev *dev)
629 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
631 b43_read32(dev, B43_MMIO_MACCTL);
634 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
638 B43_WARN_ON(dev->dev->core_rev < 3);
644 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
645 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
648 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
650 b43_time_lock(dev);
651 b43_tsf_write_locked(dev, tsf);
652 b43_time_unlock(dev);
656 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
665 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
669 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
672 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
675 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
678 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
686 bssid = dev->wl->bssid;
687 mac = dev->wl->mac_addr;
689 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
700 b43_ram_write(dev, 0x20 + i, tmp);
704 static void b43_upload_card_macaddress(struct b43_wldev *dev)
706 b43_write_mac_bssid_templates(dev);
707 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
710 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
714 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
716 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
722 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
726 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
728 b43_set_slot_time(dev, 9);
731 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
733 b43_set_slot_time(dev, 20);
739 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
741 struct b43_phy *phy = &dev->phy;
761 b43_ram_write(dev, i * 4, buffer[i]);
763 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
765 if (dev->dev->core_rev < 11)
766 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
768 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
771 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
774 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
776 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
777 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
779 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
780 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
781 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
782 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
785 ; /*b43_nphy_pa_override(dev, false) */
791 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
794 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
797 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
799 b43_read16(dev, B43_MMIO_TXE0_AUX);
802 b43_radio_write16(dev, 0x0051, 0x0017);
804 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
810 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
816 value = b43_read16(dev, B43_MMIO_IFSSTAT);
822 b43_radio_write16(dev, 0x0051, 0x0037);
825 static void key_write(struct b43_wldev *dev,
834 kidx = b43_kidx_to_fw(dev, index);
836 b43_shm_write16(dev, B43_SHM_SHARED,
840 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
844 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
848 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
853 if (b43_new_kidx_api(dev))
875 b43_shm_write32(dev, B43_SHM_RCMTA,
877 b43_shm_write16(dev, B43_SHM_RCMTA,
898 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
908 if (b43_new_kidx_api(dev))
920 if (b43_debug(dev, B43_DBG_KEYS)) {
921 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
927 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
930 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
931 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
941 struct b43_wldev *dev;
950 dev = wl->current_dev;
951 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
953 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
955 rx_tkip_phase1_write(dev, index, iv32, phase1key);
959 keymac_write(dev, index, sta->addr);
962 static void do_key_write(struct b43_wldev *dev,
969 if (b43_new_kidx_api(dev))
972 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
976 keymac_write(dev, index, NULL); /* First zero out mac. */
987 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
989 rx_tkip_phase1_write(dev, index, 0, NULL);
992 key_write(dev, index, algorithm, buf);
994 keymac_write(dev, index, mac_addr);
996 dev->key[index].algorithm = algorithm;
999 static int b43_key_write(struct b43_wldev *dev,
1019 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
1021 B43_WARN_ON(dev->key[i].keyconf == keyconf);
1025 if (b43_new_kidx_api(dev))
1032 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
1033 if (!dev->key[i].keyconf) {
1040 b43warn(dev->wl, "Out of hardware key memory\n");
1046 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1047 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1050 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1053 dev->key[index].keyconf = keyconf;
1058 static int b43_key_clear(struct b43_wldev *dev, int index)
1060 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1062 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1064 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1065 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1068 dev->key[index].keyconf = NULL;
1073 static void b43_clear_keys(struct b43_wldev *dev)
1077 if (b43_new_kidx_api(dev))
1082 b43_key_clear(dev, i);
1085 static void b43_dump_keymemory(struct b43_wldev *dev)
1095 if (!b43_debug(dev, B43_DBG_KEYS))
1098 hf = b43_hf_read(dev);
1099 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1101 if (b43_new_kidx_api(dev)) {
1109 key = &(dev->key[index]);
1112 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1114 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1118 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1127 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1131 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1133 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1144 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1178 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1187 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1189 b43_read32(dev, B43_MMIO_MACCTL);
1190 if (awake && dev->dev->core_rev >= 5) {
1193 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1203 void b43_wireless_core_phy_pll_reset(struct b43_wldev *dev)
1208 switch (dev->dev->bus_type) {
1211 bcma_cc = &dev->dev->bdev->bus->drv_cc;
1221 ssb_cc = &dev->dev->sdev->bus->chipco;
1233 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1238 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1241 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1244 b43_phy_take_out_of_reset(dev);
1247 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1258 b43_device_enable(dev, flags);
1260 if (dev->phy.type == B43_PHYTYPE_AC) {
1263 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1266 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1268 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1270 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1272 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1274 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1277 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1278 b43_bcma_phy_reset(dev);
1279 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
1284 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1292 if (dev->phy.type == B43_PHYTYPE_N)
1294 b43_device_enable(dev, flags);
1297 b43_phy_take_out_of_reset(dev);
1301 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1305 switch (dev->dev->bus_type) {
1308 b43_bcma_wireless_core_reset(dev, gmode);
1313 b43_ssb_wireless_core_reset(dev, gmode);
1322 if (dev->phy.ops)
1323 dev->phy.ops->switch_analog(dev, 1);
1325 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1330 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1333 static void handle_irq_transmit_status(struct b43_wldev *dev)
1340 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1343 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1357 b43_handle_txstatus(dev, &stat);
1361 static void drain_txstatus_queue(struct b43_wldev *dev)
1365 if (dev->dev->core_rev < 5)
1371 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1374 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1378 static u32 b43_jssi_read(struct b43_wldev *dev)
1382 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
1384 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
1389 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1391 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1393 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1397 static void b43_generate_noise_sample(struct b43_wldev *dev)
1399 b43_jssi_write(dev, 0x7F7F7F7F);
1400 b43_write32(dev, B43_MMIO_MACCMD,
1401 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1404 static void b43_calculate_link_quality(struct b43_wldev *dev)
1408 if (dev->phy.type != B43_PHYTYPE_G)
1410 if (dev->noisecalc.calculation_running)
1412 dev->noisecalc.calculation_running = true;
1413 dev->noisecalc.nr_samples = 0;
1415 b43_generate_noise_sample(dev);
1418 static void handle_irq_noise(struct b43_wldev *dev)
1420 struct b43_phy_g *phy = dev->phy.g;
1428 if (dev->phy.type != B43_PHYTYPE_G)
1440 B43_WARN_ON(!dev->noisecalc.calculation_running);
1441 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1447 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1448 i = dev->noisecalc.nr_samples;
1453 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1454 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1455 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1456 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1457 dev->noisecalc.nr_samples++;
1458 if (dev->noisecalc.nr_samples == 8) {
1463 average += dev->noisecalc.samples[i][j];
1469 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1480 dev->stats.link_noise = average;
1481 dev->noisecalc.calculation_running = false;
1485 b43_generate_noise_sample(dev);
1488 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1490 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1494 b43_power_saving_ctl_bits(dev, 0);
1496 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1497 dev->dfq_valid = true;
1500 static void handle_irq_atim_end(struct b43_wldev *dev)
1502 if (dev->dfq_valid) {
1503 b43_write32(dev, B43_MMIO_MACCMD,
1504 b43_read32(dev, B43_MMIO_MACCMD)
1506 dev->dfq_valid = false;
1510 static void handle_irq_pmq(struct b43_wldev *dev)
1517 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1522 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1525 static void b43_write_template_common(struct b43_wldev *dev,
1535 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1542 b43_ram_write(dev, ram_offset, tmp);
1552 b43_ram_write(dev, ram_offset + i - 2, tmp);
1554 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1561 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1572 if (dev->phy.gmode)
1573 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1575 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1605 static void b43_write_beacon_template(struct b43_wldev *dev,
1620 spin_lock_irqsave(&dev->wl->beacon_lock, flags);
1621 info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1622 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1624 beacon_skb = skb_clone(dev->wl->current_beacon, GFP_ATOMIC);
1625 spin_unlock_irqrestore(&dev->wl->beacon_lock, flags);
1628 b43dbg(dev->wl, "Could not upload beacon. "
1637 b43_write_template_common(dev, (const u8 *)bcn,
1643 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1653 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1683 b43_shm_write16(dev, B43_SHM_SHARED,
1685 b43_shm_write16(dev, B43_SHM_SHARED,
1696 b43_shm_write16(dev, B43_SHM_SHARED,
1699 b43_shm_write16(dev, B43_SHM_SHARED,
1702 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1707 static void b43_upload_beacon0(struct b43_wldev *dev)
1709 struct b43_wl *wl = dev->wl;
1713 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
1717 static void b43_upload_beacon1(struct b43_wldev *dev)
1719 struct b43_wl *wl = dev->wl;
1723 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
1727 static void handle_irq_beacon(struct b43_wldev *dev)
1729 struct b43_wl *wl = dev->wl;
1740 dev->irq_mask &= ~B43_IRQ_BEACON;
1742 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1748 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1749 dev->irq_mask |= B43_IRQ_BEACON;
1757 b43_upload_beacon0(dev);
1758 b43_upload_beacon1(dev);
1759 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1761 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1764 b43_upload_beacon0(dev);
1765 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1767 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1769 b43_upload_beacon1(dev);
1770 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1772 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1777 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1779 u32 old_irq_mask = dev->irq_mask;
1782 handle_irq_beacon(dev);
1783 if (old_irq_mask != dev->irq_mask) {
1785 B43_WARN_ON(!dev->irq_mask);
1786 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1787 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1802 struct b43_wldev *dev;
1805 dev = wl->current_dev;
1806 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1807 if (b43_bus_host_is_sdio(dev->dev)) {
1809 b43_do_beacon_update_trigger_work(dev);
1812 b43_do_beacon_update_trigger_work(dev);
1852 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1854 b43_time_lock(dev);
1855 if (dev->dev->core_rev >= 3) {
1856 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1857 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1859 b43_write16(dev, 0x606, (beacon_int >> 6));
1860 b43_write16(dev, 0x610, beacon_int);
1862 b43_time_unlock(dev);
1863 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1866 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1871 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1872 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1876 b43dbg(dev->wl, "The panic reason is unknown.\n");
1885 b43_controller_restart(dev, "Microcode panic");
1890 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1897 if (!dev->fw.opensource)
1901 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1905 b43_handle_firmware_panic(dev);
1912 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1916 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1919 b43info(dev->wl, "Shared memory dump:\n");
1927 b43info(dev->wl, "Microcode register dump:\n");
1929 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1944 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1946 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1948 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1953 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1958 b43_shm_write16(dev, B43_SHM_SCRATCH,
1962 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1965 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1969 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1972 reason = dev->irq_reason;
1974 dma_reason[i] = dev->dma_reason[i];
1979 b43err(dev->wl, "MAC transmission error\n");
1982 b43err(dev->wl, "PHY transmission error\n");
1984 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1985 atomic_set(&dev->phy.txerr_cnt,
1987 b43err(dev->wl, "Too many PHY TX errors, "
1989 b43_controller_restart(dev, "PHY TX errors");
1994 b43err(dev->wl,
1999 b43err(dev->wl, "This device does not support DMA "
2002 dev->use_pio = true;
2003 b43_controller_restart(dev, "DMA error");
2008 handle_irq_ucode_debug(dev);
2010 handle_irq_tbtt_indication(dev);
2012 handle_irq_atim_end(dev);
2014 handle_irq_beacon(dev);
2016 handle_irq_pmq(dev);
2021 handle_irq_noise(dev);
2026 b43warn(dev->wl, "RX descriptor underrun\n");
2027 b43_dma_handle_rx_overflow(dev->dma.rx_ring);
2030 if (b43_using_pio_transfers(dev))
2031 b43_pio_rx(dev->pio.rx_queue);
2033 b43_dma_rx(dev->dma.rx_ring);
2042 handle_irq_transmit_status(dev);
2045 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2048 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2049 dev->irq_count++;
2050 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2052 dev->irq_bit_count[i]++;
2061 struct b43_wldev *dev = dev_id;
2063 mutex_lock(&dev->wl->mutex);
2064 b43_do_interrupt_thread(dev);
2065 mutex_unlock(&dev->wl->mutex);
2070 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
2077 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2080 reason &= dev->irq_mask;
2084 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
2086 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
2088 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2090 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2092 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2095 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2100 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2101 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2102 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2103 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2104 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2105 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2107 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2111 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2113 dev->irq_reason = reason;
2121 struct b43_wldev *dev = dev_id;
2124 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2127 spin_lock(&dev->wl->hardirq_lock);
2128 ret = b43_do_interrupt(dev);
2129 spin_unlock(&dev->wl->hardirq_lock);
2135 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2137 struct b43_wl *wl = dev->wl;
2142 ret = b43_do_interrupt(dev);
2144 b43_do_interrupt_thread(dev);
2156 static void b43_release_firmware(struct b43_wldev *dev)
2158 complete(&dev->fw_load_complete);
2159 b43_do_release_fw(&dev->fw.ucode);
2160 b43_do_release_fw(&dev->fw.pcm);
2161 b43_do_release_fw(&dev->fw.initvals);
2162 b43_do_release_fw(&dev->fw.initvals_band);
2184 complete(&ctx->dev->fw_load_complete);
2231 init_completion(&ctx->dev->fw_load_complete);
2233 ctx->dev->dev->dev, GFP_KERNEL,
2239 wait_for_completion(&ctx->dev->fw_load_complete);
2247 ctx->dev->dev->dev);
2298 struct b43_wldev *dev = ctx->dev;
2299 struct b43_firmware *fw = &ctx->dev->fw;
2300 struct b43_phy *phy = &dev->phy;
2301 const u8 rev = ctx->dev->dev->core_rev;
2393 switch (dev->phy.type) {
2453 switch (dev->phy.type) {
2517 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2523 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2529 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2540 b43_release_firmware(dev);
2544 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2545 static void b43_one_core_detach(struct b43_bus_dev *dev);
2552 struct b43_wldev *dev = wl->current_dev;
2561 ctx->dev = dev;
2583 b43err(dev->wl, "%s", errmsg);
2585 b43_print_fw_helptext(dev->wl, 1);
2590 if (!modparam_qos || dev->fw.opensource)
2606 static int b43_upload_microcode(struct b43_wldev *dev)
2608 struct wiphy *wiphy = dev->wl->hw->wiphy;
2617 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2620 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2623 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2625 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2628 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2629 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2630 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2632 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2636 if (dev->fw.pcm.data) {
2638 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2639 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2640 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2641 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2643 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2645 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2650 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2653 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2659 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2664 b43err(dev->wl, "Microcode not responding\n");
2665 b43_print_fw_helptext(dev->wl, 1);
2671 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2674 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2675 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2676 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2677 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2680 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2683 b43_print_fw_helptext(dev->wl, 1);
2687 dev->fw.rev = fwrev;
2688 dev->fw.patch = fwpatch;
2689 if (dev->fw.rev >= 598)
2690 dev->fw.hdr_format = B43_FW_HDR_598;
2691 else if (dev->fw.rev >= 410)
2692 dev->fw.hdr_format = B43_FW_HDR_410;
2694 dev->fw.hdr_format = B43_FW_HDR_351;
2695 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
2697 dev->qos_enabled = dev->wl->hw->queues > 1;
2699 dev->hwcrypto_enabled = true;
2701 if (dev->fw.opensource) {
2705 dev->fw.patch = fwtime;
2706 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2707 dev->fw.rev, dev->fw.patch);
2709 fwcapa = b43_fwcapa_read(dev);
2710 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2711 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2713 dev->hwcrypto_enabled = false;
2718 b43info(dev->wl, "Loading firmware version %u.%u "
2723 if (dev->fw.pcm_request_failed) {
2724 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2726 b43_print_fw_helptext(dev->wl, 0);
2731 dev->fw.rev, dev->fw.patch);
2732 wiphy->hw_version = dev->dev->core_id;
2734 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2737 b43warn(dev->wl, "You are using an old firmware image. "
2740 b43_print_fw_helptext(dev->wl, 0);
2747 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2753 static int b43_write_initvals(struct b43_wldev *dev,
2782 b43_write32(dev, offset, value);
2795 b43_write16(dev, offset, value);
2808 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2809 b43_print_fw_helptext(dev->wl, 1);
2814 static int b43_upload_initvals(struct b43_wldev *dev)
2818 struct b43_firmware *fw = &dev->fw;
2825 return b43_write_initvals(dev, ivals, count,
2829 static int b43_upload_initvals_band(struct b43_wldev *dev)
2833 struct b43_firmware *fw = &dev->fw;
2843 return b43_write_initvals(dev, ivals, count,
2852 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2854 struct ssb_bus *bus = dev->dev->sdev->bus;
2857 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2859 return bus->chipco.dev;
2864 static int b43_gpio_init(struct b43_wldev *dev)
2871 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2872 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2876 if (dev->dev->chip_id == 0x4301) {
2879 } else if (dev->dev->chip_id == 0x5354) {
2885 b43_write16(dev, B43_MMIO_GPIO_MASK,
2886 b43_read16(dev, B43_MMIO_GPIO_MASK)
2895 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2897 b43_write16(dev, B43_MMIO_GPIO_MASK,
2898 b43_read16(dev, B43_MMIO_GPIO_MASK)
2904 switch (dev->dev->bus_type) {
2907 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
2912 gpiodev = b43_ssb_gpio_dev(dev);
2925 static void b43_gpio_cleanup(struct b43_wldev *dev)
2931 switch (dev->dev->bus_type) {
2934 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
2939 gpiodev = b43_ssb_gpio_dev(dev);
2948 void b43_mac_enable(struct b43_wldev *dev)
2950 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2953 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2957 b43err(dev->wl, "b43_mac_enable(): The firmware "
2963 dev->mac_suspended--;
2964 B43_WARN_ON(dev->mac_suspended < 0);
2965 if (dev->mac_suspended == 0) {
2966 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
2967 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2970 b43_read32(dev, B43_MMIO_MACCTL);
2971 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2972 b43_power_saving_ctl_bits(dev, 0);
2977 void b43_mac_suspend(struct b43_wldev *dev)
2983 B43_WARN_ON(dev->mac_suspended < 0);
2985 if (dev->mac_suspended == 0) {
2986 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2987 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
2989 b43_read32(dev, B43_MMIO_MACCTL);
2991 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2998 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
3003 b43err(dev->wl, "MAC suspend failed\n");
3006 dev->mac_suspended++;
3010 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3014 switch (dev->dev->bus_type) {
3017 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3022 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3027 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3032 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3039 void b43_mac_switch_freq(struct b43_wldev *dev, u8 spurmode)
3041 u16 chip_id = dev->dev->chip_id;
3046 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x1862);
3047 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3050 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x3e70);
3051 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3054 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x6666);
3055 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3067 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x2082);
3068 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3071 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x5341);
3072 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3075 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x8889);
3076 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3079 } else if (dev->phy.type == B43_PHYTYPE_LCN) {
3082 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x7CE0);
3083 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3086 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0xCCCD);
3087 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3093 static void b43_adjust_opmode(struct b43_wldev *dev)
3095 struct b43_wl *wl = dev->wl;
3099 ctl = b43_read32(dev, B43_MMIO_MACCTL);
3127 if (dev->dev->core_rev <= 4)
3130 b43_write32(dev, B43_MMIO_MACCTL, ctl);
3134 if (dev->dev->chip_id == 0x4306 &&
3135 dev->dev->chip_rev == 3)
3140 b43_write16(dev, 0x612, cfp_pretbtt);
3147 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
3149 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
3152 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
3163 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
3164 b43_shm_read16(dev, B43_SHM_SHARED, offset));
3167 static void b43_rate_memory_init(struct b43_wldev *dev)
3169 switch (dev->phy.type) {
3175 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
3176 b43_rate_memory_write(dev, B43_OFDM_RATE_9MB, 1);
3177 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
3178 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
3179 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
3180 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
3181 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
3182 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
3185 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3186 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3187 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3188 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3196 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3204 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3205 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3206 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3210 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3218 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3220 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3222 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3224 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3228 static void b43_chip_exit(struct b43_wldev *dev)
3230 b43_phy_exit(dev);
3231 b43_gpio_cleanup(dev);
3238 static int b43_chip_init(struct b43_wldev *dev)
3240 struct b43_phy *phy = &dev->phy;
3247 if (dev->phy.gmode)
3250 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3252 err = b43_upload_microcode(dev);
3256 err = b43_gpio_init(dev);
3260 err = b43_upload_initvals(dev);
3264 err = b43_upload_initvals_band(dev);
3269 phy->ops->switch_analog(dev, 1);
3270 err = b43_phy_init(dev);
3276 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3280 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3281 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3284 value16 = b43_read16(dev, 0x005E);
3286 b43_write16(dev, 0x005E, value16);
3288 b43_write32(dev, 0x0100, 0x01000000);
3289 if (dev->dev->core_rev < 5)
3290 b43_write32(dev, 0x010C, 0x01000000);
3292 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3293 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3297 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
3300 b43_adjust_opmode(dev);
3302 if (dev->dev->core_rev < 3) {
3303 b43_write16(dev, 0x060E, 0x0000);
3304 b43_write16(dev, 0x0610, 0x8000);
3305 b43_write16(dev, 0x0604, 0x0000);
3306 b43_write16(dev, 0x0606, 0x0200);
3308 b43_write32(dev, 0x0188, 0x80000000);
3309 b43_write32(dev, 0x018C, 0x02000000);
3311 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3312 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
3313 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3314 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3315 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3316 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3317 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3319 b43_mac_phy_clock_set(dev, true);
3321 switch (dev->dev->bus_type) {
3325 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3330 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3331 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3337 b43dbg(dev->wl, "Chip initialized\n");
3342 b43_gpio_cleanup(dev);
3346 static void b43_periodic_every60sec(struct b43_wldev *dev)
3348 const struct b43_phy_operations *ops = dev->phy.ops;
3351 ops->pwork_60sec(dev);
3354 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3357 static void b43_periodic_every30sec(struct b43_wldev *dev)
3360 b43_calculate_link_quality(dev);
3363 static void b43_periodic_every15sec(struct b43_wldev *dev)
3365 struct b43_phy *phy = &dev->phy;
3368 if (dev->fw.opensource) {
3371 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3373 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3374 b43_controller_restart(dev, "Firmware watchdog");
3377 b43_shm_write16(dev, B43_SHM_SCRATCH,
3383 phy->ops->pwork_15sec(dev);
3389 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3392 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3393 dev->irq_count / 15,
3394 dev->tx_count / 15,
3395 dev->rx_count / 15);
3396 dev->irq_count = 0;
3397 dev->tx_count = 0;
3398 dev->rx_count = 0;
3399 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3400 if (dev->irq_bit_count[i]) {
3401 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3402 dev->irq_bit_count[i] / 15, i, (1 << i));
3403 dev->irq_bit_count[i] = 0;
3410 static void do_periodic_work(struct b43_wldev *dev)
3414 state = dev->periodic_state;
3416 b43_periodic_every60sec(dev);
3418 b43_periodic_every30sec(dev);
3419 b43_periodic_every15sec(dev);
3429 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3431 struct b43_wl *wl = dev->wl;
3436 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3438 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3441 do_periodic_work(dev);
3443 dev->periodic_state++;
3445 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3449 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3454 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3456 struct delayed_work *work = &dev->periodic_work;
3458 dev->periodic_state = 0;
3460 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3464 static int b43_validate_chipaccess(struct b43_wldev *dev)
3468 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3469 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3472 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3473 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3475 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3476 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3481 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3482 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3483 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3484 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3485 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3486 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3487 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3488 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3489 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3490 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3491 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3492 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3494 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3495 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3497 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3500 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3501 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3502 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3504 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3507 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3509 v = b43_read32(dev, B43_MMIO_MACCTL);
3516 b43err(dev->wl, "Failed to validate the chipaccess\n");
3520 static void b43_security_init(struct b43_wldev *dev)
3522 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3526 dev->ktp *= 2;
3528 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3530 b43_clear_keys(dev);
3537 struct b43_wldev *dev;
3541 dev = wl->current_dev;
3542 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3543 *data = b43_read16(dev, B43_MMIO_RNG);
3585 struct b43_wldev *dev;
3591 dev = wl->current_dev;
3592 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3600 if (b43_using_pio_transfers(dev))
3601 err = b43_pio_tx(dev, skb);
3603 err = b43_dma_tx(dev, skb);
3620 dev->tx_count++;
3646 static void b43_qos_params_upload(struct b43_wldev *dev,
3654 if (!dev->qos_enabled)
3657 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3671 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3675 b43_shm_write16(dev, B43_SHM_SHARED,
3679 b43_shm_write16(dev, B43_SHM_SHARED,
3696 static void b43_qos_upload_all(struct b43_wldev *dev)
3698 struct b43_wl *wl = dev->wl;
3702 if (!dev->qos_enabled)
3708 b43_mac_suspend(dev);
3711 b43_qos_params_upload(dev, &(params->p),
3714 b43_mac_enable(dev);
3762 static void b43_qos_init(struct b43_wldev *dev)
3764 if (!dev->qos_enabled) {
3766 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3767 b43_write16(dev, B43_MMIO_IFSCTL,
3768 b43_read16(dev, B43_MMIO_IFSCTL)
3770 b43dbg(dev->wl, "QoS disabled\n");
3775 b43_qos_upload_all(dev);
3778 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3779 b43_write16(dev, B43_MMIO_IFSCTL,
3780 b43_read16(dev, B43_MMIO_IFSCTL)
3782 b43dbg(dev->wl, "QoS enabled\n");
3790 struct b43_wldev *dev;
3804 dev = wl->current_dev;
3805 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3809 b43_mac_suspend(dev);
3810 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3812 b43_mac_enable(dev);
3836 struct b43_wldev *dev;
3840 dev = wl->current_dev;
3842 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3843 b43_tsf_read(dev, &tsf);
3856 struct b43_wldev *dev;
3859 dev = wl->current_dev;
3861 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3862 b43_tsf_write(dev, tsf);
3882 static int b43_switch_band(struct b43_wldev *dev,
3885 struct b43_phy *phy = &dev->phy;
3903 b43err(dev->wl, "This device doesn't support %s-GHz band\n",
3913 b43dbg(dev->wl, "Switching to %s GHz band\n",
3918 b43_software_rfkill(dev, true);
3921 b43_phy_put_into_reset(dev);
3922 switch (dev->dev->bus_type) {
3925 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3930 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3935 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3940 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3944 b43_phy_take_out_of_reset(dev);
3946 b43_upload_initvals_band(dev);
3948 b43_phy_init(dev);
3953 static void b43_set_beacon_listen_interval(struct b43_wldev *dev, u16 interval)
3956 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BCN_LI, interval);
3960 static void b43_set_retry_limits(struct b43_wldev *dev,
3969 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3971 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3978 struct b43_wldev *dev = wl->current_dev;
3979 struct b43_phy *phy = &dev->phy;
3985 b43_mac_suspend(dev);
3988 b43_set_beacon_listen_interval(dev, conf->listen_interval);
3995 err = b43_switch_band(dev, conf->chandef.chan);
4002 b43_switch_channel(dev, phy->channel);
4006 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
4012 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
4018 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
4025 b43_mgmtframe_txantenna(dev, antenna);
4028 phy->ops->set_rx_antenna(dev, antenna);
4032 b43_software_rfkill(dev, false);
4033 b43info(dev->wl, "Radio turned on by software\n");
4034 if (!dev->radio_hw_enable) {
4035 b43info(dev->wl, "The hardware RF-kill button "
4040 b43_software_rfkill(dev, true);
4041 b43info(dev->wl, "Radio turned off by software\n");
4046 b43_mac_enable(dev);
4052 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
4055 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
4089 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
4092 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
4103 struct b43_wldev *dev;
4107 dev = wl->current_dev;
4108 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4120 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
4128 b43_write_mac_bssid_templates(dev);
4131 b43_mac_suspend(dev);
4139 b43_set_beacon_int(dev, conf->beacon_int);
4142 b43_update_basic_rates(dev, conf->basic_rates);
4146 b43_short_slot_timing_enable(dev);
4148 b43_short_slot_timing_disable(dev);
4151 b43_mac_enable(dev);
4161 struct b43_wldev *dev;
4186 dev = wl->current_dev;
4188 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4191 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4236 err = b43_key_write(dev, -1, algorithm,
4241 err = b43_key_write(dev, index, algorithm,
4249 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4251 b43_hf_write(dev,
4252 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4259 err = b43_key_clear(dev, key->hw_key_idx);
4274 b43_dump_keymemory(dev);
4286 struct b43_wldev *dev;
4289 dev = wl->current_dev;
4290 if (!dev) {
4311 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4312 b43_adjust_opmode(dev);
4319 * Returns the current dev. This might be different from the passed in dev,
4321 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4328 if (!dev)
4330 wl = dev->wl;
4332 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4333 return dev;
4337 cancel_delayed_work_sync(&dev->periodic_work);
4339 b43_leds_stop(dev);
4341 dev = wl->current_dev;
4342 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4344 return dev;
4348 b43_set_status(dev, B43_STAT_INITIALIZED);
4349 if (b43_bus_host_is_sdio(dev->dev)) {
4351 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4352 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4355 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4356 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4360 orig_dev = dev;
4362 if (b43_bus_host_is_sdio(dev->dev))
4363 b43_sdio_free_irq(dev);
4365 free_irq(dev->dev->irq, dev);
4367 dev = wl->current_dev;
4368 if (!dev)
4369 return dev;
4370 if (dev != orig_dev) {
4371 if (b43_status(dev) >= B43_STAT_STARTED)
4373 return dev;
4375 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4388 b43_mac_suspend(dev);
4389 b43_leds_exit(dev);
4392 return dev;
4396 static int b43_wireless_core_start(struct b43_wldev *dev)
4400 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4402 drain_txstatus_queue(dev);
4403 if (b43_bus_host_is_sdio(dev->dev)) {
4404 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4406 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4410 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4412 IRQF_SHARED, KBUILD_MODNAME, dev);
4414 b43err(dev->wl, "Cannot request IRQ-%d\n",
4415 dev->dev->irq);
4421 ieee80211_wake_queues(dev->wl->hw);
4422 b43_set_status(dev, B43_STAT_STARTED);
4425 b43_mac_enable(dev);
4426 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4429 b43_periodic_tasks_setup(dev);
4431 b43_leds_init(dev);
4433 b43dbg(dev->wl, "Wireless interface started\n");
4438 static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4468 static int b43_phy_versioning(struct b43_wldev *dev)
4470 struct b43_phy *phy = &dev->phy;
4471 const u8 core_rev = dev->dev->core_rev;
4483 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4535 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4536 analog_type, phy_type, b43_phy_name(dev, phy_type),
4540 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4541 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
4547 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 0);
4548 radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4550 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 1);
4551 radio_id = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4558 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4559 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4567 if (dev->dev->chip_id == 0x4317) {
4568 if (dev->dev->chip_rev == 0)
4570 else if (dev->dev->chip_rev == 1)
4575 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4577 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4578 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4580 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
4627 b43err(dev->wl,
4632 b43info(dev->wl,
4648 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4662 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4664 dev->dfq_valid = false;
4668 dev->radio_hw_enable = true;
4671 memset(&dev->stats, 0, sizeof(dev->stats));
4673 setup_struct_phy_for_init(dev, &dev->phy);
4676 dev->irq_reason = 0;
4677 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4678 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4680 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4682 dev->mac_suspended = 1;
4685 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4688 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4690 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4697 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4700 hf = b43_hf_read(dev);
4705 b43_hf_write(dev, hf);
4708 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4715 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4721 if (dev->dev->bus_type != B43_BUS_SSB)
4727 bus = dev->dev->sdev->bus;
4731 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4735 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4740 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4746 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4748 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4751 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4755 static void b43_set_pretbtt(struct b43_wldev *dev)
4760 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
4764 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4765 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4770 static void b43_wireless_core_exit(struct b43_wldev *dev)
4772 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4773 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4776 b43_set_status(dev, B43_STAT_UNINIT);
4779 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4782 switch (dev->dev->bus_type) {
4785 bcma_host_pci_down(dev->dev->bdev->bus);
4795 b43_dma_free(dev);
4796 b43_pio_free(dev);
4797 b43_chip_exit(dev);
4798 dev->phy.ops->switch_analog(dev, 0);
4799 if (dev->wl->current_beacon) {
4800 dev_kfree_skb_any(dev->wl->current_beacon);
4801 dev->wl->current_beacon = NULL;
4804 b43_device_disable(dev, 0);
4805 b43_bus_may_powerdown(dev);
4809 static int b43_wireless_core_init(struct b43_wldev *dev)
4811 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4812 struct b43_phy *phy = &dev->phy;
4816 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4818 err = b43_bus_powerup(dev, 0);
4821 if (!b43_device_is_enabled(dev))
4822 b43_wireless_core_reset(dev, phy->gmode);
4825 setup_struct_wldev_for_init(dev);
4826 phy->ops->prepare_structs(dev);
4829 switch (dev->dev->bus_type) {
4832 bcma_host_pci_irq_ctl(dev->dev->bdev->bus,
4833 dev->dev->bdev, true);
4834 bcma_host_pci_up(dev->dev->bdev->bus);
4839 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4840 dev->dev->sdev);
4845 b43_imcfglo_timeouts_workaround(dev);
4846 b43_bluetooth_coext_disable(dev);
4848 err = phy->ops->prepare_hardware(dev);
4852 err = b43_chip_init(dev);
4855 b43_shm_write16(dev, B43_SHM_SHARED,
4856 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4857 hf = b43_hf_read(dev);
4874 if (dev->dev->bus_type == B43_BUS_SSB &&
4875 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4876 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4880 b43_hf_write(dev, hf);
4883 if (dev->dev->core_rev >= 13) {
4884 u32 mac_hw_cap = b43_read32(dev, B43_MMIO_MAC_HW_CAP);
4886 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_L,
4888 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_H,
4892 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4894 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4895 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4901 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4903 b43_rate_memory_init(dev);
4904 b43_set_phytxctl_defaults(dev);
4908 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4910 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4912 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4915 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYTYPE, phy->type);
4916 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYVER, phy->rev);
4918 if (b43_bus_host_is_pcmcia(dev->dev) ||
4919 b43_bus_host_is_sdio(dev->dev)) {
4920 dev->__using_pio_transfers = true;
4921 err = b43_pio_init(dev);
4922 } else if (dev->use_pio) {
4923 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4926 dev->__using_pio_transfers = true;
4927 err = b43_pio_init(dev);
4929 dev->__using_pio_transfers = false;
4930 err = b43_dma_init(dev);
4934 b43_qos_init(dev);
4935 b43_set_synth_pu_delay(dev, 1);
4936 b43_bluetooth_coext_enable(dev);
4938 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4939 b43_upload_card_macaddress(dev);
4940 b43_security_init(dev);
4942 ieee80211_wake_queues(dev->wl->hw);
4944 b43_set_status(dev, B43_STAT_INITIALIZED);
4950 b43_chip_exit(dev);
4952 b43_bus_may_powerdown(dev);
4953 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4961 struct b43_wldev *dev;
4979 dev = wl->current_dev;
4985 b43_adjust_opmode(dev);
4986 b43_set_pretbtt(dev);
4987 b43_set_synth_pu_delay(dev, 0);
4988 b43_upload_card_macaddress(dev);
5004 struct b43_wldev *dev = wl->current_dev;
5016 b43_adjust_opmode(dev);
5018 b43_upload_card_macaddress(dev);
5026 struct b43_wldev *dev = wl->current_dev;
5045 if (b43_status(dev) < B43_STAT_INITIALIZED) {
5046 err = b43_wireless_core_init(dev);
5052 if (b43_status(dev) < B43_STAT_STARTED) {
5053 err = b43_wireless_core_start(dev);
5056 b43_wireless_core_exit(dev);
5082 struct b43_wldev *dev = wl->current_dev;
5086 if (!dev)
5090 if (b43_status(dev) >= B43_STAT_STARTED) {
5091 dev = b43_wireless_core_stop(dev);
5092 if (!dev)
5095 b43_wireless_core_exit(dev);
5129 struct b43_wldev *dev;
5132 dev = wl->current_dev;
5133 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5135 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
5144 struct b43_wldev *dev;
5147 dev = wl->current_dev;
5148 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5150 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
5159 struct b43_wldev *dev = wl->current_dev;
5167 survey->noise = dev->stats.link_noise;
5200 struct b43_wldev *dev =
5202 struct b43_wl *wl = dev->wl;
5208 prev_status = b43_status(dev);
5211 dev = b43_wireless_core_stop(dev);
5212 if (!dev) {
5218 b43_wireless_core_exit(dev);
5222 err = b43_wireless_core_init(dev);
5227 err = b43_wireless_core_start(dev);
5229 b43_wireless_core_exit(dev);
5235 wl->current_dev = NULL; /* Failed to init the dev. */
5251 static int b43_setup_bands(struct b43_wldev *dev,
5254 struct ieee80211_hw *hw = dev->wl->hw;
5255 struct b43_phy *phy = &dev->phy;
5268 if (dev->phy.type == B43_PHYTYPE_N) {
5278 dev->phy.supports_2ghz = have_2ghz_phy;
5279 dev->phy.supports_5ghz = have_5ghz_phy;
5284 static void b43_wireless_core_detach(struct b43_wldev *dev)
5288 b43_release_firmware(dev);
5289 b43_phy_free(dev);
5292 static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy,
5298 if (dev->dev->bus_type == B43_BUS_BCMA &&
5299 dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI)
5300 dev_id = dev->dev->bdev->bus->host_pci->device;
5303 if (dev->dev->bus_type == B43_BUS_SSB &&
5304 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5305 dev_id = dev->dev->sdev->bus->host_pci->device;
5308 if (dev->dev->bus_sprom->dev_id)
5309 dev_id = dev->dev->bus_sprom->dev_id;
5332 if (dev->phy.type != B43_PHYTYPE_G)
5351 switch (dev->phy.type) {
5365 static int b43_wireless_core_attach(struct b43_wldev *dev)
5367 struct b43_wl *wl = dev->wl;
5368 struct b43_phy *phy = &dev->phy;
5380 err = b43_bus_powerup(dev, 0);
5389 switch (dev->dev->bus_type) {
5392 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5399 if (dev->dev->core_rev >= 5) {
5400 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5409 dev->phy.gmode = have_2ghz_phy;
5410 b43_wireless_core_reset(dev, dev->phy.gmode);
5413 err = b43_phy_versioning(dev);
5418 b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy);
5422 switch (dev->phy.type) {
5437 err = b43_phy_allocate(dev);
5441 dev->phy.gmode = have_2ghz_phy;
5442 b43_wireless_core_reset(dev, dev->phy.gmode);
5444 err = b43_validate_chipaccess(dev);
5447 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5453 wl->current_dev = dev;
5454 INIT_WORK(&dev->restart_work, b43_chip_reset);
5456 dev->phy.ops->switch_analog(dev, 0);
5457 b43_device_disable(dev, 0);
5458 b43_bus_may_powerdown(dev);
5464 b43_phy_free(dev);
5466 b43_bus_may_powerdown(dev);
5470 static void b43_one_core_detach(struct b43_bus_dev *dev)
5477 wldev = b43_bus_get_wldev(dev);
5481 b43_bus_set_wldev(dev, NULL);
5485 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5495 wldev->dev = dev;
5505 b43_bus_set_wldev(dev, wldev);
5547 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5551 ssb_set_devtypedata(dev->sdev, NULL);
5556 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5558 struct ssb_sprom *sprom = dev->bus_sprom;
5590 SET_IEEE80211_DEV(hw, dev->dev);
5612 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5614 dev->core_rev);
5621 struct b43_bus_dev *dev;
5631 dev = b43_bus_dev_bcma_init(core);
5632 if (!dev)
5635 wl = b43_wireless_init(dev);
5641 err = b43_one_core_attach(dev, wl);
5654 kfree(dev);
5676 b43_one_core_detach(wldev->dev);
5683 kfree(wldev->dev);
5698 struct b43_bus_dev *dev;
5702 dev = b43_bus_dev_ssb_init(sdev);
5703 if (!dev)
5715 wl = b43_wireless_init(dev);
5723 err = b43_one_core_attach(dev, wl);
5734 b43_wireless_exit(dev, wl);
5736 kfree(dev);
5744 struct b43_bus_dev *dev = wldev->dev;
5759 b43_one_core_detach(dev);
5765 b43_wireless_exit(dev, wl);
5766 kfree(dev);
5778 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5781 if (b43_status(dev) < B43_STAT_INITIALIZED)
5783 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5784 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);