Lines Matching defs:ctl
1614 u16 ctl;
1643 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1645 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1646 ctl &= ~B43_TXH_PHY_ANT;
1647 ctl &= ~B43_TXH_PHY_ENC;
1648 ctl |= antenna;
1650 ctl |= B43_TXH_PHY_ENC_CCK;
1652 ctl |= B43_TXH_PHY_ENC_OFDM;
1653 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3096 u32 ctl;
3099 ctl = b43_read32(dev, B43_MMIO_MACCTL);
3101 ctl &= ~B43_MACCTL_AP;
3102 ctl &= ~B43_MACCTL_KEEP_CTL;
3103 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
3104 ctl &= ~B43_MACCTL_KEEP_BAD;
3105 ctl &= ~B43_MACCTL_PROMISC;
3106 ctl &= ~B43_MACCTL_BEACPROMISC;
3107 ctl |= B43_MACCTL_INFRA;
3111 ctl |= B43_MACCTL_AP;
3113 ctl &= ~B43_MACCTL_INFRA;
3116 ctl |= B43_MACCTL_KEEP_CTL;
3118 ctl |= B43_MACCTL_KEEP_BAD;
3120 ctl |= B43_MACCTL_KEEP_BADPLCP;
3122 ctl |= B43_MACCTL_BEACPROMISC;
3128 ctl |= B43_MACCTL_PROMISC;
3130 b43_write32(dev, B43_MMIO_MACCTL, ctl);
3133 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
3146 if (0 /* ctl & B43_MACCTL_AP */)
3198 u16 ctl = 0;
3200 ctl |= B43_TXH_PHY_ENC_CCK;
3201 ctl |= B43_TXH_PHY_ANT01AUTO;
3202 ctl |= B43_TXH_PHY_TXPWR;
3204 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3205 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3206 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);