Lines Matching defs:rev
55 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
56 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
76 /* PIO on core rev < 11 */
85 /* PIO on core rev >= 11 */
93 #define B43_MMIO_RADIO24_CONTROL 0x3D8 /* core rev >= 24 only */
94 #define B43_MMIO_RADIO24_DATA 0x3DA /* core rev >= 24 only */
125 #define B43_MMIO_XMTFIFO_FRAME_CNT 0x522 /* core rev>= 16 only */
126 #define B43_MMIO_XMTFIFO_BYTE_CNT 0x524 /* core rev>= 16 only */
127 #define B43_MMIO_XMTFIFO_HEAD 0x526 /* core rev>= 16 only */
128 #define B43_MMIO_XMTFIFO_RD_PTR 0x528 /* core rev>= 16 only */
129 #define B43_MMIO_XMTFIFO_WR_PTR 0x52A /* core rev>= 16 only */
130 #define B43_MMIO_XMTFIFODEF1 0x52C /* core rev>= 16 only */
139 #define B43_MMIO_SMPL_CLCT_STRPTR 0x552 /* core rev>= 22 only */
140 #define B43_MMIO_SMPL_CLCT_STPPTR 0x554 /* core rev>= 22 only */
141 #define B43_MMIO_SMPL_CLCT_CURPTR 0x556 /* core rev>= 22 only */
152 #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */
153 #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */
154 #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */
155 #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */
231 B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */
282 #define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */
368 #define B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */
385 #define B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
387 #define B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */
388 #define B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */
389 #define B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */
390 #define B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */
391 #define B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
392 #define B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */
520 #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */
521 #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
527 #define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */
528 #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */
529 #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */
791 u16 rev;
803 * core rev > 10, as these don't need PCM firmware. */